DP83867E: Trying to understand the SFD Variation

Mark Graham

Part Number: DP83867E

Hello

I am looking at the Start of Frame detection timing for 1000-Mb. For Transmit the variation is 0. For Receive when a master the variation is +-4ns. I'd like to understand where this variation comes from and if there is any way of reducing it by slewing clocks or some other way. My guess it is because the SFD pin is asserted clocked by the Tx clock but I could be wrong.

Thanks

Mark

over 8 years ago

0 Aniruddha Khadye over 8 years ago

TI__Mastermind 18425 points

Hello Mark,

Did you get a chance to review the "SFD Latency Variation and Determinism" section of the datasheet? It lists the steps needed for improving determinism in SFD latency.

-Regards,
Aniruddha

0 Mark Graham over 8 years ago in reply to Aniruddha Khadye

Prodigy 245 points

Yes I read that section.

My interpretation is that you use that information in order to get to the specs listed in 7.11

I am trying to understand where the +-4ns comes from in the Master Receive timing and if there is any way to reduce it external to the PHY.

Thanks

Mark

0 Aniruddha Khadye over 8 years ago in reply to Mark Graham

TI__Mastermind 18425 points

Hello Mark,

The variation is due to the internal operation of ADC and the phase interpolator. Just by the nature of PHY's working, it won't be possible to reduce the variation more than the datasheet limits.

-Regards,
Aniruddha

0 Mark Graham over 8 years ago in reply to Aniruddha Khadye

Prodigy 245 points

Thank you. I can't figure why there is no variation at the slave end, but it is what it is.

Thank you.

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DP83867E: Trying to understand the SFD Variation