Other Parts Discussed in Thread: DS90UH947-Q1
Dear Team,
our customer is facing a problem with the I2C of the 947/8:
When the main controller is communicating via I2C with the LVDS chips, the LVDS chips can keep the SDA line low for the remaining time that the chip is powered when the I2C transfer was not finished.
This situation is visible in the below image where the last byte is the slave address of the LVDS serializer chip.
SCL is pulled back to high by the master later in time but the SDA remains low.
Do the LVDS 947/948 chips have a slave timeout that releases the SDA line when an I2C transfer is not finished within a certain period?
Looking forward to your answer.
Best Regards
Martin
