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DP83640: How to align the phase of the clock output in the sync ethernet mode?

xiaoP
Intellectual 365 points
Part Number: DP83640


Conditions: two 83640, connect by the cable. I make one of them sync ethernet mode by setting the SYNC_ENET_EN bit of the PHYCR2. 

the two clock output(GPIO 12) locked, but the phase is random when power up. I didn't run the PTP stack.

I notice that file AN-1729 3.2, about Phase Alignment. 

I checked EPL\protocol\PTP\ptpControl.c line 272 to 312, which Rob told me: The function starts with the comment // Phase align CLKOUT if requested

That function appears to implement the phase alignment procedure detailed in AN-1729. 

The question is ：before one step adjustment to the 1588 clock time, everything goes right. I get the event timestamps, checked PTP_ESTS, Calculate the phase error. 

But the one step adjustment is not working（I compare the delay between the two clock output by oscilloscope）……

I'm wondering whether I can use phase alignment in sync ethernet mode. I think 83640 should support.

So the reason is I didn't run the 1588 stack?  But I think I have already got the event timestamps , and  just add phase error to the clock it should work. I don;t think it need the stack running, is it right？ 

 Or as long as the 1588 clock running, it needs the stack. I'm a little confused……

  • 0
    TI__Mastermind 19780 points
    Hi xiaoP,

    I am not sure what your problem is right now. Are you saying that the clock phase adjustment does not work on the DP83640 with the SyncE mode enabled?

    Thanks,
  • 0 in reply to Rob Rodrigues
    Intellectual 365 points
    Thank god you answer me, Rob!
    Yes, phase adjustment does not work and I don't know why .
    I try to make it clearly:
    I don't run the ptpd stack, my code is just similar to function PTPInitHardware, and I do phase adjustment in slave board.
    I watch the two clock outputs(master and slave ) phase by oscilloscope, and phase adjustment does not work .

    my question:
    1、Does phase adjustment need ptpd stack running? I don't think so. Because the master and slave are already Synchronous. In addition the code EPL\protocol\PTP\ptpControl.c line 272 to 312 in function PTPInitHardware , at this time , the ptpd stack is not running.

    2、whether the phase of 2 clock outputs(GPIO 12) can be alignment through a step adjustment (reg PTP_TDR) to the 1588 clock time.
    In Synchronous Ethernet Mode the PTP logic (PTP clock and PTP counter) between master and slave are locked. But there is random phase error when power up. I don’t think do a step adjustment (reg PTP_TDR) can align this kind phase error. The PTP clock is the source of clock output, and Divide-by N. I don’t find any explain about phase config between PTP clock and clock output or PTP clock and PTP counter in TI file. You can’t do phase adjust(PTP clock) by change the PTP counter.

    I also find some similar questions on E2E, for reference.
    e2e.ti.com/.../413987
    I think this may be a common problem. I look foward somebody can help us.
  • 0 in reply to xiaoP
    TI__Mastermind 23675 points
    Hi XiaoP,

    We are reviewing your question and will get back to you.

    Best regards,
    Ross
  • 0 in reply to Ross Pimentel
    Intellectual 365 points

    thank you Ross, looking forward to your reply