Please teach me Three questions.
① We will use DP83867 IR at 1000 M (GMII).
Please tell us about the recommended connections (TX_CLK, CLK_OUT, 25 MHZ).
Please see the attached document.
An example of connection between FPGA and PHY (excerpt from ALTERA - FPGA - Ether manual).
In this connection, 25 MHz is multiplied by 5 and connected to TX_CLK,
Is it possible to connect CLK_OUT to 125 MHZ in the DP83867?
Or would you prefer to enter 25 Mhz and make it five times larger with PLL?
② TX_CLK is written for MII (10 M, 100 M).
If we use only 1000 M, this terminal does not have to be connected?
(Can I open it?)
Is it OK if CLK_OUT is not used yet?
③ I think that it will operate in RGMII mode when the power is turned on.
Is it enough to change the RGMII ENABLE register (0x0032) to 0x0 to switch to GMII mode?
Or is it necessary to make other settings?
