Hi,
We are bringing up a new design prototype which is utilising the XI3130 PCIe switch and are having some problems controlling the downstream REFCK enable controls.
The design does not utiltise any hot plug control signals downstream, and two downstream NIC devices are held in reset via GPIO until the operating system has booted. The intent was to initiate a downstream hot reset to initiate a new training sequence once software has enabled the GPIO control.
The problem we have is that following power on, where the downstream clocks can be seem for a brief period and are then disabled, we cannot re-eanble the clocks under software control. After booting the OS, issueing a SRST via the bridge control register has no affect as the clocks are not operational.
I assume there is something else gating the enabling of the clocks, but cannot ascertain the cause. All error registers are reporting okay, and we have toggled the REFCK_EN control in the slot's general control registers to no effect.
Any guidance would be appreciated.
Sincerely
John Weston
