• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 33 subscribers
  • Views 836 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83867IS: DP83867ISRGZ SGMII_COP, SGMII_CON question

Sammi Shang
Expert 4450 points
Part Number: DP83867IS

Dear team, 

For SGMII mode, 

If  only use 4-wire , MAC will recover clock from the data received, how about the clock frequency? And the clock level Vpp?

If use 6-wire, will PHY provide 625MHZ clock to MAC? How about the Vpp?

Another question,

Customer use Xlinx XC7Z030F+TI DP83867ISRGZ, if use SGMII mode, need FPGA  support 625MHz?

Thanks.

Best regards,

Sammi

  • 0
    TI__Mastermind 19780 points
    Hi Sammi,

    If only use 4-wire , MAC will recover clock from the data received, how about the clock frequency? And the clock level Vpp?
    The clock frequency will be recovered from the DP83867 data stream and will have the same frequency. The clock level is something internal to the MAC, this will not be measurable.

    If use 6-wire, will PHY provide 625MHZ clock to MAC? How about the Vpp?
    Yes, the PHY will provide 625MHz clock on the COP, CON pins. The Vpp will meet the LVDS spec as defined by the SGMII standard.

    I am not familiar with the Xilinx XC7Z030F. What is your question? I did not understand what you meant.

    Best Regards,