• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 2 answers
  • Subscribers 32 subscribers
  • Views 1000 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN65DSI84: PLL_UNLOCK always 1

Kermith Galang
Prodigy 50 points
Part Number: SN65DSI84

Hi All,

I am having problem with SN65DSI84,

here is the setup

Test pattern is now working

when test pattern is disabled, only black screen

all registers are configured:

PLL_EN_STAT = 1

PLL_UNLOCK = 0x01

My question is, is the PLL_UNLOCK related or possible cause of problem why there are 

no display ?

  • 0
    TI__Mastermind 18655 points
    Hello Kermith Galang ,

    The PLL_UNLOCK is the CLK issue. You have to check if this bit is being set back to 1 after it’s cleared. If you continue detecting the PLL_UNLOCK error, the input CLK has a signal integrity issue.
    I can help you to review the device configuration. Please, use the DSI Tuner to configure your panel and export the .dsi file. Besides this file please share the panel datasheet and your schematics.

    Regards,
    Joel
  • 0 in reply to Joel Jimenez0
    Prodigy 50 points
    HI Joel

    yes, after being cleared, this returns to 1. can you tell me more about the signal integrity issue.

    thanks for your time, I will send the schematic and panel datasheet tomorrow, but for now, is it something related to
    LVDS_CLK_RANGE
    DSI_CLK_DIVIDER
    CHA_DSI_CLK_RANGE


    currently, my dsi clock outputs 420MHz while my LVDS panel accepts around 70Mhz
    which I currently set them to
    010 – 62.5 MHz ≤ LVDS_CLK < 87.5 MHz
    Divide by 6
    and 420< freq <425

    Regards,
  • 0 in reply to Kermith Galang
    TI__Mastermind 18655 points
    Hello Kermith,

    Is the DSI clock running HS continuous? Is the LVDS clock running at 70MHz?

    Regards
  • 0 in reply to Joel Jimenez0
    Prodigy 50 points
    Hi Jose Jimenez,

    yes the DSI clock is running HS continuous at 420Mhz, also LVDS is running at 70Mhz,

    fortunately, the display is working following the DSI tuner configuration, still I am confuse
    1. dsi output is working if the active line is set to 1920, but the test pattern is always black
    2. when the active line is set to 960, dsi is black, but the test pattern was ok.
  • 0 in reply to Kermith Galang
    TI__Mastermind 18655 points

    Hello Kermith,

    Glad to know that it is working.  In pattern mode, the CHA_ACTIVE_LINE_LENGTH filed corresponds to the pixels length that will output to the each LVDS channel individually. In other words, it should be configured with the half of the total active line length.

    Regards