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TCA9555: TCA9555: What kinds of thing would happen during communication with master when master is reset?

Nanfang Liao
Intellectual 2085 points
Part Number: TCA9555

Hello Team,

I meet the same problem of our TCA9555. I2C host connects two TCA9555s and communicate the I2C slaves of the two TCA9555s circularly. During the time I2C host is reset, sometimes one TCA9555 is freezed, and the Data BUS of I2C is pulled low. Now I2C host will be reset and communicate again, they find the I2C host can only communicate with one TCA9555.

Do you have any comments about this problem? Thanks

cid:image002.jpg@01D327E5.7251BDB0

Regards,

Nanfang

  • 0
    TI__Mastermind 20905 points
    Hello Nanfang,
    It looks like you meant to post an image but I don't see it. Can you post it.
    -Francis Houde
  • 0
    TI__Mastermind 20905 points
    Hello Nanfang,
    Can you get me a schematic of the design so I can review.
    Waveforms of the SCL and SDA lines as this occurs would also be helpful.
    -Francis Houde
  • 0 in reply to fhoude
    TI__Intellectual 2085 points

    Hello Team,

    The test waveform is as below, thanks

    Regards,

    Nanfang

  • 0 in reply to Nanfang Liao
    TI__Guru 62920 points
    Hi Nanfang,

    When the host is reset, does TCA9555 remain powered? Do either of the I2C lines get pulled low, or do they remain high during the reset? There is a strange spike on SDA after I would expect an ACK from the first byte - do you know what is causing that?

    If you toggle SCL many times after this happens, will SDA eventually release?

    Max
  • 0 in reply to Miguel Robertson
    TI__Intellectual 2085 points
    Hello Max,

    Thanks for your quick response, below are my input, please help to give your comments.

    When the host is reset, does TCA9555 remain powered?
    Yes, TCA9555 remain powered, and we also tested the power supply, it is OK

    Do either of the I2C lines get pulled low, or do they remain high during the reset?
    During the reset, we can find I2C bus get pulled low and last about ~ms time.

    There is a strange spike on SDA after I would expect an ACK from the first byte - do you know what is causing that?
    I think when releasing I2C bus and I2C master and slave can't be controlled, which cause this spike.

    If you toggle SCL many times after this happens, will SDA eventually release?
    Yes, I2C bus can recover and master can communicate other slaves of good TCA9555

    Regards,
    Nanfang
  • 0 in reply to Nanfang Liao
    TI__Guru 62920 points
    Nanfang,

    It sounds like the I2C state machine in TCA9555 may be getting out of sync because the SDA/SCL lines are toggling during reset and these toggles are being interpreted as data. Is it possible to create at least nine SCL clock cycles whenever the MCU comes out of RESET so that any buses that are stuck can recover before data transmission is needed? Then you should make sure to initiate communication with a START command and terminate it with a STOP command.

    Max