SN65DSI83： SN85DSI83 Initialize abnormal.

xingxing Luo

Part Number: SN65DSI83

Hi Sir:

I had use the SN65DSI83 on Qualcomm msm8909 platform, and the SN65DSI83 i2c work normal, I had used the DSI Tuner (V2.0) which download from IT web, but when I write the CSR to the chip, the PLL lock failed, and I debug the chip on test mode, and the screen was black, the attachment was the LCD datasheet and the CSR values.

static int sn65dsi83_pll_en(int enable)

{

int retval = 0,count = 0;

char pll_en;

TI_INFO("%s,enable=%d\n",__func__,enable);

if(enable)

{

retval = sn65dsi83_i2c_write(PLL_ADDR,PLL_LOCK_DATA);

if(retval < 0)

{

TI_ERROR("set pll en failed.");

return retval;

}else

{

TI_ERROR("set pll en sccess.");

}

sn65dsi83_i2c_read(PLL_CHECK_LOCK,&pll_en,sizeof(pll_en));

TI_INFO("pll lock = 0x%02x.",pll_en);

while(!(pll_en & 1 << PLL_LOCK_MASK) && count < 50)

{

msleep(2);

count++;

sn65dsi83_i2c_read(PLL_CHECK_LOCK,&pll_en,sizeof(pll_en));

}

if(count == 50)

{

TI_ERROR("lock pll failed.");

return -1;

}

else

{

retval = sn65dsi83_i2c_write(SOFT_RESET_ADDR,SOFT_RESET_DATA);

if(retval < 0)

{

TI_ERROR(" reset ic fail\n"); return retval;

}

retval = sn65dsi83_i2c_write(PLL_ADDR,PLL_LOCK_DATA);

if(retval < 0)

{

TI_ERROR("set pll en fail\n"); r

eturn retval; }

}

else

{

retval = sn65dsi83_i2c_write(PLL_ADDR,PLL_UNLOCK_DATA);

if(retval < 0)

{

TI_ERROR("set pll disable fail\n");

return retval;

}

return retval;

}

The abnormal log:

[ 4.431122] <<-sn65dsi83->> sn65dsi83_init_chip start.

[ 4.439079] i2c-msm-v2 78b7000.i2c: msm_bus_scale_register_client(mstr-id:86):0x7 (ok)

[ 4.459515] <<-sn65dsi83->> sn65dsi83_init_config success.

[ 4.459515]

[ 4.467557] <<-sn65dsi83->> sn65dsi83_pll_en,enable=1

[ 4.467557]

[ 4.473457] <<-sn65dsi83->> set pll en sccess.

[ 4.477858] <<-sn65dsi83->> pll lock = 0x01.

[ 5.472744] <<-sn65dsi83->> lock pll failed.

[ 5.475988] <<-sn65dsi83->> ti_sn65dsi83_pll_en failed.

[ 5.475988] [ 5.482766] <<-sn65dsi83->> sn65dsi83_chip_init failed.

There still some question here:

1. How can I make sure the LCD's LVDS_HPW and LVDS_VPM;

2. How can I make sure the LCD's Additional Panel info from the LCD datasheet.

Fullscreen 2438.CSR-HPW10.txt Download

//=====================================================================
// Filename   : CSR-HPW10.txt
//
//   (C) Copyright 2013 by Texas Instruments Incorporated.
//   All rights reserved.
//
//=====================================================================
0x09              0x00
0x0A              0x01
0x0B              0x00
0x0D              0x00
0x10              0x26
0x11              0x00
0x12              0x00
0x13              0x00
0x18              0x7a
0x19              0x00
0x1A              0x03
0x1B              0x00
0x20              0x00
0x21              0x05
0x22              0x00
0x23              0x00
0x24              0xd0
0x25              0x02
0x26              0x00
0x27              0x00
0x28              0x20
0x29              0x00
0x2A              0x00
0x2B              0x00
0x2C              0x0a
0x2D              0x00
0x2E              0x00
0x2F              0x00
0x30              0x0a
0x31              0x00
0x32              0x00
0x33              0x00
0x34              0x20
0x35              0x00
0x36              0x03
0x37              0x00
0x38              0x20
0x39              0x00
0x3A              0x03
0x3B              0x00
0x3C              0x10
0x3D              0x00
0x3E              0x00


The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet

Fullscreen CSR-HPW10.txt Download

//=====================================================================
// Filename   : CSR-HPW10.txt
//
//   (C) Copyright 2013 by Texas Instruments Incorporated.
//   All rights reserved.
//
//=====================================================================
0x09              0x00
0x0A              0x01
0x0B              0x00
0x0D              0x00
0x10              0x26
0x11              0x00
0x12              0x00
0x13              0x00
0x18              0x7a
0x19              0x00
0x1A              0x03
0x1B              0x00
0x20              0x00
0x21              0x05
0x22              0x00
0x23              0x00
0x24              0xd0
0x25              0x02
0x26              0x00
0x27              0x00
0x28              0x20
0x29              0x00
0x2A              0x00
0x2B              0x00
0x2C              0x0a
0x2D              0x00
0x2E              0x00
0x2F              0x00
0x30              0x0a
0x31              0x00
0x32              0x00
0x33              0x00
0x34              0x20
0x35              0x00
0x36              0x03
0x37              0x00
0x38              0x20
0x39              0x00
0x3A              0x03
0x3B              0x00
0x3C              0x10
0x3D              0x00
0x3E              0x00


The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet

HSD080IHW1-A10 Preliminary Specification 1.0.pdf

over 8 years ago

0 Joel Jimenez0 over 8 years ago

TI__Mastermind 18655 points

Hello xingxing,

Please, use DSI Tuner to export the .dsi file. This will help us to check all your parameters easily. Please, check if your LVDS output clock is running at the correct frequency with the correct levels. (58.7MHz)

Try configuring LVDS_HPW = 1, LVDS_HBP = 32 , LVDS_HFP = 31, LVDS_VPW= 1, LVDS_VBP=3 and LVDS_VBP = 2.

Regards,
Joel

0 xingxing Luo over 8 years ago in reply to Joel Jimenez0

Prodigy 130 points

Hi Joel:

Thanks for your help, I had followed your suggestion, and I will try it later, and how can I get the Additional Panel info.

and the attachment was the .dsi file which take your suggestion.

hpw_1.dsi.zip

0 xingxing Luo over 8 years ago in reply to Joel Jimenez0

Prodigy 130 points

Hi Joel:

I had update my .dsi file.and I didn't have the device to check the LDVS clk.

PS: I had debug on test mode.CSR-0912.zip

0 Joel Jimenez0 over 8 years ago in reply to xingxing Luo

TI__Mastermind 18655 points

Hello xingxing Luo,
Have you tried configuring Format 2?
What is the DSI Clk frequency? Configure it in the DSI Tuner
Regards

0 xingxing Luo over 7 years ago in reply to Joel Jimenez0

Prodigy 130 points

Hi Joel:

My DSI CLK is 351MHz, and I divided by 5, the LVDS CLK is 70.2MHz, and now the 0xE5 register value is 0x31 after start the video stream, then the value is 0x01 that I read in the interrupt, the log as following:

[ 4.448073] <<-sn65dsi83->> sn65dsi83_init_chip start.

[ 4.463261] <<-sn65dsi83->> sn65dsi83_init_config

[ 4.468020] i2c-msm-v2 78b7000.i2c: msm_bus_scale_register_client(mstr-id:86):0x7 (ok)

[ 4.488358] <<-sn65dsi83->> sn65dsi83_init_config success.

[ 4.488358]

[ 4.499394] <<-sn65dsi83->> sn65dsi83_pll_en,enable=1

[ 4.499394] [ 4.505300] <<-sn65dsi83->> set pll en sccess.

[ 4.509704] <<-sn65dsi83->> pll lock = 0x85.

[ 4.513892] <<-sn65dsi83->> sn65dsi83_pll_en: SW reset ic OK.

[ 4.519633] <<-sn65dsi83->> sn65dsi83_read_clk.

[ 4.540023] <<-sn65dsi83->> Read PLL_CHECK_LOCK success:0x85.

[ 4.544741] <<-sn65dsi83->> LVDS_CLK data:0x02.

[ 4.549255] <<-sn65dsi83->> LVDS_CLK bits: 010

[ 4.553772] The LVDS clock range is:62.5MHz~87.5MHz

[ 4.558369] <<-sn65dsi83->> sn65dsi83_pll_en success.

[ 4.558369]

[ 4.575141] <<-sn65dsi83->> sn65dsi83_test.

[ 4.590020] <<-sn65dsi83->> Read CHA_XXX_ERR_E5 success: 0x31.

[ 4.625341] <<-sn65dsi83->> sn65dsi83_work_func.

[ 4.625687] <<-sn65dsi83->> sn65dsi83_work_func 0xe5 = 31

[ 4.625687]

[ 4.625942] <<-sn65dsi83->> sn65dsi83_work_func.

[ 4.626243] <<-sn65dsi83->> sn65dsi83_work_func 0xe5 = 1

[ 4.626243] [ 4.626485] <<-sn65dsi83->> sn65dsi83_work_func.

[ 4.626787] <<-sn65dsi83->> sn65dsi83_work_func 0xe5 = 1

[ 4.626787] [ 4.627148] <<-sn65dsi83->> sn65dsi83_work_func.

[ 4.627478] <<-sn65dsi83->> sn65dsi83_work_func 0xe5 = 1

[ 4.627478] [ 4.627967] <<-sn65dsi83->> sn65dsi83_work_func.

[ 4.628296] <<-sn65dsi83->> sn65dsi83_work_func 0xe5 = 1

[ 4.628296] [ 4.628644] <<-sn65dsi83->> sn65dsi83_work_func.

[ 4.628972] <<-sn65dsi83->> sn65dsi83_work_func 0xe5 = 1

It means that PLL unlock, how can I resolve the problem, did you have any suggestion.

0 Joel Jimenez0 over 7 years ago in reply to xingxing Luo

TI__Mastermind 18655 points

Hello xingxing Luo,
Suggest clearing the interrupt and then read back to see if error only occurs once or if it occurs all the (time this field is cleared by writing '1'). If these errors are occurring all the time, then they need to check the timing on DSI channel An interface (setup/hold). Maybe they can change DSI85 RXEQ level (register 0x11) to see if errors go away.
Please, also verify whether the flag is being set when the test pattern is enabled.

Regards

Interface

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SN65DSI83： SN85DSI83 Initialize abnormal.