Part Number: DP83867E
Hello
I am trying to interpret the below statement in the DP83867 datasheet.
I am trying to understand if the TxClock is locked to the Rx clock in the slave, or whether the TxClock is locked to the Local clock in the slave.
The reason I need to know is:
I'd like to take the Slave's ClkOut pin (based off one of the Rx lanes), clean it and feed it into the Slave's ClkIn pin. In this case I will have a certain phase shift between Tx and Rx at my Master device. I'd then like to add some phase delay at the ClkIn pin of the slave. Will this additional phase delay then be seen between the Tx and Rx data at the master?
This is the wording in the datasheet:
8.3.3 Clock Output
The DP83867 has several internal clocks, including the local reference clock, the Ethernet transmit clock, and the
Ethernet receive clock. An external crystal or oscillator provides the stimulus for the local reference clock. The
local reference clock acts as the central source for all clocking in the device.
The local reference clock is embedded into the transmit network packet traffic and is recovered from the network
packet traffic at the receiver node. The receive clock is recovered from the received Ethernet packet data stream
and is locked to the transmit clock in the partner.
Thanks
mark Graham
