Dear All,
I am experiencing some problem with the ethernet on a custom board and I am checking the connection between MAC and the PHY.
I am using DP83620 with RMII interface in master mode. The 25 MHz clock from the CPU crystal is provided to the X1 pin of the PHY, through a CLK_OUT pin of the CPU.
Now the RMII MAC requires the following signals - other than MDIO and MDC - (look for instance to SNLA076A for the DP83848 Table 1):
REF_CLK
TX_EN
TXD[0]
TXD[1]
RXD[0]
RXD[1]
CRS_DV
Now, looking at the datasheet (par 6.2.1) it seems that for RMII (Master Mode) the signals CLK_OUT, RX_CLK and TX_CLK has to be routed to the MAC while for RMII (Slave Mode), the datasheet (par 6.2.2) says: "RX_CLK, TX_CLK, and CLK_OUT should not be used as the RMII reference clock in this mode but may be used for other system devices.": what does it means?
In my board (PHY configured in RMII Master Mode) the RX_CLK is routed to the REF_CLK of the MAC. Is this correct? I wonder if it is correct to say that RX_CLK and TX_CLK signal are synchronous with CLK_OUT.
Thank you.
