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DS110DF1610: REF_MODE

Darren Jenkins
Genius 12571 points
Part Number: DS110DF1610
Other Parts Discussed in Thread: DS125DF1610

Team,

One of our customers is using the DS110DF1610.  They are observing that the setting for REF_MODE in 0x36 is set to b00 after reset (referenceless).  These bits are supposed to be b11 after reset according to the datasheet.  Do you have any explanation for how these bits could be b00?

Even after they change the setting to b11, it does not help achieve a reliable lock.  Sometimes it takes hours to lock.  Other times, it locks and shows high BER.  Is this related to the REF_MODE bits being set wrong?

Thanks,

Darren

  • 0
    TI__Mastermind 23675 points
    Hi Darren,

    Moving this to another forum for more visibility.

    Best regards,
    Ross
  • 0
    TI__Mastermind 19235 points

    Can you confirm the customer is first selecting the channel registers as per below?

    Table. Shared-Channel Select Global Register

    GLOBAL REGISTER

    BIT

    DESCRIPTION

    0xFF

    7:2

    These bits are not used and default to 0

    1

    1: Broadcast write to all channels, 0xFF[0] must be set to 1.

    0: Normal operation, select channel register as defined in 0xFC and 0xFD

    0

    1: Select Channel Registers

    0: Select Share Registers

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • 0 in reply to Rodrigo Natal
    Prodigy 150 points
    Hello Rodrigo,

    Thank you very much for getting back.

    We are selecting Channel registers correctly. We are manufacturing device based on DS125DF1610 part for more then a Year. One of our customers requested support for 8.5Gbps rate, so we built for them a limited batch with DS110DF1610 part. The devices are identical except just one part.

    We have modified a little initialization routine to take into account minor differences between the parts. RefClk default frequency (25Mhz vs 125Mhz) etc. Devices with DS110DF1610 are behaving differently. Unable to lock for hours on particular channels, significantly lower HEO. I dumped default values for channel registers for both parts and found REF mode bits difference.
    Setting these bits to "1" is not helping.

    Today we replaced DS110 with DS125 on one board (we have 4 chips per board) and it started to work as expected. All channels are locking immediately with HEO > 0.81, VEO > 300mv (Externally supplied by FPGA PRBS 31 Pattern).

    Thanks !

    Best Regards,
    Sergey Sardaryan
  • 0 in reply to Maria Sukiasyan
    TI__Mastermind 19235 points

    Hi. Some additional things to try:

    • Make sure the CDR rate is being programmed correctly
      • Stadnard rate settings can be applied via channel register 0x2F
      • If the appllication data rate is not one of the retimer standard rates, custom rates can be programmed via channel registers 0x60 - 0x63
    • Try stetting 0x3A to 0x00 on DS110DF1610
    • On DS110DF1610, channel register 0x36 should be set to 0x30
    • As a troubleshooting exercise, you may try to disabling some CDR lock qualifiers on the DS110DF1610 to see if CDR locks
      • Disable Single Bit Transition check by setting 0x0C[3]=0
      • Disable ppm check by setting 0x2F[2]=0
      • Disable FLD check by setting 0x2F[1]=0

    Regards,

    Rodrigo Natal

    HSSC Applications Engineer