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Thanks for your great question! I will look into this and update you asap.
can you tell me about your application?
what trace are you wanting to widen? IN+/IN-?
as well as you want to keep the same distance (as used on the EVM) for the decoupling caps from the IC to VCC1 and VCC2?
The caps are placed this way on the UCC53xxEVM to allow a socket to be installed for internal use. When laying out decoupling caps please refer to the DS layout guidelines.