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DP83867IR: DP83867IR strapping + cable side connections

David Kusnerak
Prodigy 90 points
Part Number: DP83867IR
Other Parts Discussed in Thread: DP83867ERGZ-R-EVM

Using  DP83867IR with XE232-1000-FB374 processor. XE232 SGMII connections to RX_D0 and RX_D2 have  weak pull downs. Resistance value not provided just maximum input source/sink current of (-/+)100uA.

Q1) Is it recommended to add additional pull down resistors at the DP83867IR?

Q2) If required, what is the recommended value, 2.49K?

The physical distance between the MAC and PHY is ~1" with trace matching per DATA Sheet.

Q3) Should matching external pull down resistors be added to RD_X1 and RX_D3 nets?

RJ45 connection: New to Ethernet, The Eval board and DS both show the "TD_[P:M]_C" pair connections are inverted as compared to the other three A, B & D pairs. This is for normal operation, straight cable connections, RJ45 connector pins 5 and 4, are per dot polarity of the transformer, reversed going into the transformer cable side and not corrected, inverted a second time, on the PHY side of the transformer.

Q4) Why?

 

  • 0
    TI__Mastermind 23675 points
    Hi David,

    The DP83867IR does not support SGMII.

    In regards to your questions:

    A1) Strap pins have internal 9k ohm pull-down resistors. It is not required to add external pulls, but some people still do it for good practice.

    A2) Any pull strength to be below the VIL for that specific VDDIO is sufficient.

    A3) Matching external pulls are only needed on SGMII interface pins, but the IR does not support SGMII.

    No external resistors should be on the cable side pins. You can send us your schematic for review.

    Best regards,
    Ross
  • 0 in reply to Ross Pimentel
    Prodigy 90 points

    Q4, did not not explain well.

    Per standard 1000T RJ-45 pin-out,   Pin 5 : TP3+ and Pin 4: TP3- 

    Referring to the Data Sheet and Eval Board ref design TP3 connections are reverse from RJ-45 connector to the cable side input of XFRMR and was not  corrected at the PHY side of the XFRMR or at the PHY itself.  Resulting in TP3 signal being 180 out of phase to signals of TP1, TP2 and   TP4.

    Could not find an explanation for this and wondering why this PHY is configured this way?

  • 0 in reply to David Kusnerak
    TI__Mastermind 23675 points
    Hi David,

    I am sorry but I could not understand your question.

    What reference design are you referring to? We have a few reference boards.
    In the datasheet there is no reverse polarity image.
    The PHY supports polarity detection and correction on all channels (A, B, C and D).

    If we did change polarity on one of the designs, it might have been just to make layout easier since it doesn't matter with polarity correction capability.

    Best regards,
    Ross
  • 0 in reply to Ross Pimentel
    Prodigy 90 points
    Thank you, you answered my question.

    To try to clarify my previous question. The evaluation board is DP83867ERGZ-R-EVM.
    Referring to DP83867ERGZ User Guide, rev SNLU190–October 2015, page 12 schematic or Data sheet DP83867, rev SNLS484E –FEBRUARY 2015–REVISED MARCH 2017, page 110 schematic.
    RJ45 connector pins 2,4,6,8 are TP[1:4] minus signals.
    RJ45 pin 4 is routed into what would be the "dot" end of the XFRM while the remaining three minus signals are routed to the non-dot end of XFRM thus inverted that channel. Per your description this is corrected by the PHY polarity detection and correction feature. Need to review 802.3 section 28.
    Once again, thank you for your support