SN65DSI85: SN65DSI85 Vcore control

zhang myth

Part Number: SN65DSI85

hi TI expert,

we've following Sn65DSI85 initial question, thanks!

1. could we control EN pin to decide when Vcore generate? i think Vcore will be low when EN pin is low, is it right?

2. there's initialization sequence in SPEC table 5, could we initial CSR register firstly, and then set EN pin, it means Could we initial CSR register when chip is shutdown.

3.there's "delay 10ms" code after every I2C writting operation in example script in SPEC page 40&41, are these "delay 10ms" necessary ?

over 8 years ago

0 Joel Jimenez0 over 8 years ago

TI__Mastermind 18655 points

Hello zhang myth,

The SN65DSI85 has an internal voltage regulator which is controlled by the EN input. Therefore Vcore output is intended to monitor this internal regulator.

The EN pin should be high in order to be able to access the CSR registers.

Yes, the delay is required after PLL_EN bit is set and the minimum time is 3 ms.

Regards

0 user4945215 over 8 years ago in reply to Joel Jimenez0

Prodigy 60 points

Hi Joel

Thanks for your reply, and double check with you

1. I think the internal voltage regulator you mentioned above , just means the Vcore,the 1.2V output from Pin J8. It means we can use En pin to control the Vcore/1.2v output, right?

3. We can ignore other delay code in the example, just remain the minimum 3ms delay after PLL_EN is set. Right?

0 Joel Jimenez0 over 8 years ago in reply to user4945215

TI__Mastermind 18655 points

Hello user4945215,

Both statements are correct.

Regards

0 zhang myth over 8 years ago in reply to Joel Jimenez0

Prodigy 125 points

hi Joel,

I got it, very thanks.

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SN65DSI85: SN65DSI85 Vcore control