Other Parts Discussed in Thread: TUSB1211
Dear Team,
our customer was facing issues with a different device of another supplier and considers to use our TUSB1210 in combination with a Zynq FPGA.
The other device was failing the EMC tests (Class B) and so he asked us if we have some documents which help to have a good performing layout to avoid a 3rd HW iteration.
I saw that the data sheet has layout guidelines, but maybe there are more information / tips & tricks?
Thanks and best regards
Martin