Hi Team,
Please advise me on questions bellow.
Q1, The register address 0x02 bit 7 control enable/disable OLDI outputs
(datasheet says CMOS output but may be OLDI)
When is bit is set to disable OLDI, is I2S outputs also disabled?
Q2. If so, are there any register bits which configure Enable I2S while Disable OLDI?
Q3.The datasheet insist as bellow. But it is not clear to me.
Is this bit set to ‘0’ (Disable output) in UN-LOCK state and needed to be set to ‘1’
In order to get outputs?
LVCMOS Output Enable. Self-clearing on loss of LOCK
0: Disable, Tristate Outputs (default)
1: Enable
Mita
