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SN65DSI84-Q1: Initialization sequence

Part Number: SN65DSI84-Q1

Hi,


We are Vega Innovations Ltd and we are developing a high performance electric super car. Our prototype has been in development for the last three years and we plan to have a street drivable vehicle ready for testing and certification Q4 2017 with the ultimate goal of taking it into Production.

We are currently looking to expand into larger premises and have
Started on a 2nd prototype. There is huge potential in this project, our long-term plan is to produce mid-size vehicles, small city driving vehicles and provide conversions.

This is the link to our website. You can find detailed information there.

www.vega.lk

Our specialties also include,

High performance motor controllers
Efficient battery management system
Vehicle Control Unit
Charging Network Solution
Prototype testing

There is also a video on our Facebook page which details one of our launch tests.

https://www.facebook.com/VegaInnovations/videos/671219609715971/

 

While doing research on this, we came across your SN65DSI84-Q1. We're  using  SN65DSI84-Q1 with an NVIDIA TX2. Since the NVIDIA TX2 only has DSI outputs, we're using SN65DSI84-Q1 as the bridge.

Initialization Sequence Description
Init seq1                            After power is applied and stable, all DSI Input lanes including DSI CLK(DA x P/N, DB x P/N) MUST be driven to
                                          LP11 state.
Init seq2                            Assert the EN pin
Init seq3                            Wait for 1ms for the internal voltage regulator to stabilize
Init seq4                            Initialize all CSR registers to their appropriate values based on the implementation (The SN65DSI84-Q1 is not
                                          functional until the CSR registers are initialized)
Init seq5                             Start the DSI video stream
Init seq6                             Set the PLL_EN bit(CSR 0x0D.0)
Init seq7                             Wait for a minimum of 3 ms.
Init seq8                             Set the SOFT_RESET bit (CSR 0x09.0)

I uderstand seq 1,2 and 3. But appreciate if you can explain how seq 4,6 and 8 can be done.  How do we program the SN65DSI84-Q1 registers?

Thank you.

  • Hello Nipuna Weeratunge,

    Thanks for your message.
    As a starting point, I suggest using our DSI Tuner to configure the SN65DSI84-Q1 based on the GPU settings and panel requirements. You can export a .dsi file from the tool and we will review it.
    The internal register of the SN65DSI84-Q1 should be configured through its local I2C interface.
    Please take a look at figure 5. RESET and Initialization Timing Definition While VCC is High which describes the init sequence requirement.

    Regards
  • Hi Joel,

    Thank you for your reply. The process is a bit clearer now. 
    So if I understand this correctly, a USB to I2C converter or a microcontroller can be used to configure the registers  of the SN65DSI84-Q1.

    Furtherore, we would need to use a microcontroller or an FPGA to do the following initialization steps, correct?

    Init seq1                           After power is applied and stable, all DSI Input lanes including DSI CLK(DA x P/N, DB x P/N) MUST be driven to
                                            LP11 state.
    Init seq2                          Assert the EN pin
    Init seq3                          Wait for 1ms for the internal voltage regulator to stabilize
    Init seq4                          Initialize all CSR registers to their appropriate values based on the implementation (The SN65DSI84-Q1 is not
                                            functional until the CSR registers are initialized)
    Init seq5                          Start the DSI video stream
    Init seq6                          Set the PLL_EN bit(CSR 0x0D.0)
    Init seq7                           Wait for a minimum of 3 ms.
    Init seq8                            Set the SOFT_RESET bit (CSR 0x09.0)

    Much appreciate your wisdom in this.

    Thank you. 

  • Hello Nipuna Weeratunge,
    That is correct. Any compliant I2C master should work to interface the device registers.
    In the other hand, your FPGA should be DPHY compliant to configure the required states (LP11 or HS).
    Regards