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DP83867E: CLK_OUT divider by 5

Roel
Prodigy 200 points
Part Number: DP83867E

On page 87, the datasheet describes the function of the multiplexer setting CLK_O_SEL. The received clock can be set to be divided by 5. It's unclear whether the divide by 5 function is performed before the multiplexer function or after. If the divide by 5 takes place before the selection is made, the phase of the 25Mhz clock won't change when you go from setting 00111 to 00110 and back to 00111. If the divide takes place after the selection is made it's not guaranteed that the clock will have the same phase.

  • 0
    TI__Mastermind 26135 points
    Hello Roel,

    Thank you for using the TI forum, we will get back to you as soon as we can.
  • 0
    TI__Mastermind 18425 points
    Hi Roel,

    Can you describe the application and why the phase relation is important?

    -Regards,
    Aniruddha
  • 0 in reply to Aniruddha Khadye
    Prodigy 200 points

    Hi Aniruddha,

    I'm trying to find a way to measure the phase relation between received clock and reference clock in the PHY when its running in master mode. I hope it allows me to enhance the RX SFD determinism in master mode, as I assume that the the +/-4ns variation in the RX_SFD comes from the fact that there is a clock domain crossing from received clock to reference clock domain. CLK_OUT might allow to measure the phase relations and thereby provide a way to compensate for jitter induced by the clock domain crossing. To measure the phase will introduce an uncertainty when the the refclk is about of the same phase as the received clock. For that a 25Mhz clock would be much more convenient, but preferable I would like to change the multiplexer setting without affecting the phase.

    Roel

  • 0 in reply to Roel
    TI__Mastermind 18425 points
    Hello Roel,

    Unfortunately, this information relates to the internal operation of the PHY so it cannot be disclosed on open forum.

    -Regardsm,
    Aniruddha