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DP83867E: CLK_OUT divider by 5

Part Number: DP83867E

On page 87, the datasheet describes the function of the multiplexer setting CLK_O_SEL. The received clock can be set to be divided by 5. It's unclear whether the divide by 5 function is performed before the multiplexer function or after. If the divide by 5 takes place before the selection is made, the phase of the 25Mhz clock won't change when you go from setting 00111 to 00110 and back to 00111. If the divide takes place after the selection is made it's not guaranteed that the clock will have the same phase.