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SN65176B: Imbalanced rise/fall times when used in J1708 application

Bhavesh Tailor
Intellectual 290 points
Part Number: SN65176B
Other Parts Discussed in Thread: THVD1550, THVD1500, SN65HVD3088E, SN65HVD82

To whom it may concern,

We are using the SN65176B chip in a J1708 application as described in 'J1708 Bus Loading' section of the following TI app note:

www.ti.com/.../snla038b.pdf

When measuring the signals I noticed that there is an imbalance between Port A/B outputs when disabling the driver and relying on the termination described in this app note.  The termination is symmetrical, yet the Port A rises faster than the Port B falls when the driver is disabled.

I noticed from the datasheet that there is an imbalance in these outputs in the tPHZ and tPLZ delays, with maximums stated as 250ns and 30ns (respectively).  Based on this I have the following questions:

- Does this imbalanced delay also have something to do with the edge speed imbalance I am seeing, even though the termination on the outputs is symmetrical? 

-> If so, what specifically is the cause and do we need to compensate this externally by decreasing the value of the pull-down on Port B w.r.t the pull-up on Port A? 

-> If this is the case, could you suggest something that still meets the AM/FM interference rejection requirements of the J1708 specification?

Look forward to your response.

Many Thanks,

Bhav

  • 0
    TI__Guru 62920 points
    Bhav,

    Yes, it sounds like you have found the root cause - the SN65176B device takes much longer to disable when driving a high level compared to when driving a low level. This would distort the signal edges when used in a J1708 application. You can tune the disable times externally by decreasing pull-up/down resistance to speed up edges or by increasing resistance/adding capacitance to slow down edges. If possible, though, it would probably be easier to switch to a transceiver that has more symmetrical behavior with respect to enabling/disabling. You could consider either THVD1550 or THVD1500 (two newer RS-485 transceiver devices) as pin-to-pin replacements for the older SN65176B device. DS75176B (as mentioned in the app note) would also be an option to consider. Please let me know if you have any further questions.

    Regards,
    Max
  • 0 in reply to Miguel Robertson
    Intellectual 290 points

    Hi Max,

    Thanks for your prompt, informative response and suggestions.

    I am not keen on changing the termination on the A/B ports due to this filtering being recommended for J1708 applications.

    However, the THVD1550 chip would be something that I would like to try.

    Would you be able to send use some samples for test?

    Many Thanks,

    Bhav

  • 0 in reply to Bhavesh Tailor
    TI__Guru 62920 points
    Hi Bhav,

    Sorry for my late reply - I was out of the office on vacation through all of last week. You can request samples of this device through TI's eStore, though. Here is the direct link:

    www.ti.com/.../samplebuy

    Best regards,
    Max
  • 0 in reply to Miguel Robertson
    Intellectual 290 points

    Hi Max,

    I have received samples of the suggested THVD1550 part and it seems to improve the imbalance between the Port A and Port B.

    However, it seems that the issue I've been facing with the SN65176B maybe due to the Port A not going Hi-Z/disabling when DE is de-asserted.  Although much improved in the THVD1550 part, there is still traces of some initial drive on Port A when de-asserting the DE pin.  I would expect Port A to rise in the same way that Port B falls when DE is de-asserted given the symmetrical termination on each Port, but this is not the case.

    Attached is the schematic of the circuit under-test and screenshots from both the THVD1550 and the SN65176B chips. 

    Is there any reason why Port A struggles to go Hi-Z/disabled when DE is de-asserted?

    Look forward to your response.

    Many Thanks,

    BhavSN65176B_PortA_PortB_Imbalance.docx

  • 0 in reply to Bhavesh Tailor
    TI__Guru 62920 points
    Hi Bhavesh,

    Thanks for capturing these waveforms. We will try to set up a similar test here to confirm whether or not this is the expected behavior, and we will update you as soon as we have some results.

    Regards,
    Max
  • 0 in reply to Miguel Robertson
    TI__Guru 62920 points

    Hi Bhavesh,

    I wanted to share some updates on this.  We did confirm similar behavior when evaluating THVD1550 in our lab, and so we experimented with some other transceivers to see if there would be another device that would have more symmetrical edges upon the driver disabling.  It appears that the SN65HVD3088E device is able to maintain symmetry on the A and B lines:

    In case internal IEC ESD protection is needed, then the SN65HVD82 device could be used instead.  We also evaluated this device in our lab and saw performance that matched the above image.

    Best regards,
    Max