Other Parts Discussed in Thread: TLK105
tlk105
From the customer:
Currently in our design we pull the reset low until the boot loader releases it just after power up. Then 604ms after the power is up the boot loader will pull reset low for 502uS. At the start of the reset falling the clock is configured and is output (50MHz). 21uS after the rising edge of reset the boot loader starts communicating with the phy but does not get any response.
I have a couple questions:
When is the phy address clocked in after reset?
Do I need to let the reset go high during power on, or can I keep it in reset during power on until I need to use the phy?
