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DP83822I: Register configurations required to get 50MHz clock output from PHY to ENET controller

Part Number: DP83822I

Hello,

We are using TI DP83822 ENET RMII external Phy in our board.

Upon configuring following registers of DP83822I, it is able to generate 25MHz reference clock but RMII needs 50MHz reference clock.

Software:
1. Phy reset by enabling 15th bit of BMCR register
2. Enabling "RMII Master Mode Reference Clock: 50-MHz" as well as "Clock reference according to bits[14:12]" in "IOCTRL1" register
3. Enabling "50-MHz clock reference, CMOS-level oscillator" as well as"Enable RMII mode of operation" in "RCSR" register

Hardware Connections:
1. Clock source to PHY is 25MHz oscillator
2. RMII PHY is in master mode as mentioned in Page 29, figure 24 of DP83822I datasheet.

What are additional register configurations needs to be done to get 50MHz reference clock out from PHY to ENET Controller ?

Thanks & Regards,
Naveen B