- When performing a simulation with 60Mbps data rate (D0 signal simulated with 30MHz signal in simulation) and a 10pF capacitor at data output, the signal looks almost triangle rather than a square wave as expected.
- When the load capacitor is connected through a transmission line the signal gets worse as the transmission line is longer (for instance - 2" transmission line) and an internal ripple is added (that gets noticed with a transmission line larger than 1")
- The clock output signal on the other hand looks good at 60MHz signal
Is this the case with actual device or is this only a model problem?
