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SN65DSI86: Query on support of dual mode in DP Interface

Lalithaa Shree Brindha
Prodigy 50 points
Part Number: SN65DSI86
Other Parts Discussed in Thread: SN75LVDS82, SN65DSI83, TFP410

Hi,

SN65DSI86 IC has a eDP interface. I need to know whether it supports dual mode Display Port so that I can map the pins to HDMI Connector and use it,  instead of a Display Port.

Also is there any other ICs that convert DSI to HDMI?

  • 0
    TI__Mastermind 18655 points
    Hello Lalithaa,

    The SN65DSI86 does not support dual-mode display port.

    We have a three ICs solution to convert MIPI DSI to HDMI. Please, take a look at the link below:

    e2e.ti.com/.../261403

    Regards
  • 0 in reply to Joel Jimenez0
    Prodigy 50 points
    Thank you Joel,

    I have another query... I understood from the datasheet that this chip supports both command mode and video mode(All three sub-modes), Does it support both continuous and Discontinuous clock modes as well?

    And can I configure this chip to a 1-Lane DSI input?
  • 0 in reply to Lalithaa Shree Brindha
    TI__Mastermind 18655 points
    Hello Lalithaa,

    It depends on the selected reference clock source. When the DSI clock is used as the LVDS clock source, the D-PHY clock lane must operate in HS free-running (continuous) mode. If the REFCLK is used as the source for the LVDS Clock, it is allowed to stop the DSI Clock during the blanking period.

    Yes, the device is by default confirured to operate with one DSI lane in the CHA_DSI_LANES filed at register offset 0x10.

    Regards
  • 0 in reply to Joel Jimenez0
    Prodigy 50 points
    Hi Joel,

    1. In case of three chip solution for DSI to HDMI Conversion , SN65DSI83+SN75LVDS82+TFP410 does this support Discontinuous clk mode while using Refclk.
    2. is there any relation between DSI clk frequency and LVDS clk frequency to choose REFCLK for LVDS output clk
    3. Is writing CHA_DSI_CLK_RANGE register with the input clk frequency and giving a REFCLK is enough to configure the chip in discontinuous mode?

    Thanks in Advance!
  • 0 in reply to Lalithaa Shree Brindha
    Prodigy 50 points
    And also another query?
    Is the LVDS CLK frequency transmitted from SN65DSI83 is equal to PCLK (ie CLKOUT of SN75LVDS82) ?
  • 0 in reply to Lalithaa Shree Brindha
    TI__Mastermind 18655 points
    Hello Lalithaa,
    1.- Yes, for this solution is also allowed stop the DSI clock during the blanking period. Just keep in mind that the REFCLK should run at the correct frequency continuously to avoid the internal PLL loss of lock.
    2. - The only recommendation is that the DSI clk should be close to the selected output LVDS frequency in order to avoid overflow or underflow issues.
    3.- Correct. As a start point, I suggest using our DSI Tuner tool to configure the DSI8x based on the desired resolutions and clock configuration.
    4.- Correct. Please, take a look at the switching characteristics for further details on SN75LVDS82's timings.
    Regards