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DS90UB953-Q1: Forward channel GPIO timing

Sam Litvin
Prodigy 100 points
Part Number: DS90UB953-Q1

Hi,

    When operating the DS90UB953/DS90UB954 in synchronous clocking mode, is there a known phase relationship between the DS90UB953's GPIO (input) forward sampling clock and it's CLK_OUT?  (Assuming CLK_OUT is set to, for example 50Mhz with a REFCLK of 25Mhz)  Also, assuming 1 or two GPIOs in input mode.

    What I'm getting at is if it's possible to use CLK_OUT to synchronously transmit data to the GPIO inputs on the DS90UB953 and get a higher forward-channel GPIO bitrate rather than having to rely on the 4x oversampling of the data?

Thanks,

Sam 

  • 0
    TI__Intellectual 2010 points

    Hi Sam,

    The forward channel GPIO data is transferred together with the forward channel data, so its clock is consistent with forward channel data rate.

    In synchronous mode, for 25MHz reference clock, the forward channel rate = 2*80*25M =4Gbps, where 2 means each clock cycle has two “bits” of information, high and low; 80 comes from an internal multiplier from the PLLs. Usually the regular packet is 40bits long, and each packet only contains one bit for GPIO data, so the sampling frequency is 4Gbps/40bit = 100MHz (one GPIO). We recommend 4 times oversampling ratio, so the GPIO frequency is 25MHz as shown on the datasheet.

    Best regards,

    Cera