• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 927 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN65DSI84: can't work with external 26M clock

Haiwen Huang
Intellectual 2250 points
Part Number: SN65DSI84


Dears:

when used SN65DSI84, I  found below issue:

 when use external 26M clock, SN65DSI84 cannot output the LVDS CLK. Have checked write and ready registers are OK. Blow is the register for your RFE. Can you please help check it?  Thanks.

 

 

#ifdef SN65DSI84_NO_26M_CLK
    {0x0A, 0x05},
    {0x0B, 0x20},
#else
    {0x0A, 0x04},
    {0x0B, 0x02},
#endif

#ifdef SN65DSI84_NO_26M_CLK
    {0x12, 0x5d},
#else
    {0x12, 0x2c},
#endif

#ifdef SN65DSI84_NO_26M_CLK
    {0x28, 0xe1},
    {0x29, 0x03},
#else
    {0x28, 0x20},
    {0x29, 0x00},
#endif

21_LVDS_PANEL.pdf

  • 0
    TI__Mastermind 18655 points
    Hello Huang,
    Are they setting the PLL through the PLL_EN bit? The input clock source must be active and stable before the PLL is enabled.
    Is the LVDS Clock oscillating when the DSI Clk is selected as the source?
    Are they able to try a higher reference clock?
    Is the reference clock meeting the timing requirements (rise and fall time) stated in the device datasheet?
    Regards
  • 0 in reply to Joel Jimenez0
    TI__Intellectual 2250 points

           HI Joel:

    Here is customer inputs:

        1、Are they setting the PLL through the PLL_EN bit? The input clock source must be active and stable before the PLL is enabled.

             Yes. they follow the sequence.
        2、Is the LVDS Clock oscillating when the DSI Clk is selected as the source?

             Yes，the LVDS Clock does work
        3、Are they able to try a higher reference clock?

             customer will have a try.

        4、In regards with your schematics it seems to be configured correctly. I have only one comment: when the REFCLK is used, you do not need the pull-down resistor in this terminal.

             customer deleted  the pull-down resistor, but it didn't work  as well 。

    Can you please help check if the register configuration is OK?

  • 0 in reply to Haiwen Huang
    TI__Mastermind 18655 points
    Huang,

    The registers configuration seems correct.

    Please, send scope captures of the REFCLK.

    Could you please enable the test pattern to see if you detect the same behavior?

    Regards
  • 0 in reply to Joel Jimenez0
    TI__Intellectual 2250 points
    Hi Joel:
    Have solved this issue by use higher frequency clock. but I can't understand what happened?
  • 0 in reply to Haiwen Huang
    TI__Mastermind 18655 points
    Huang,

    What frequency solved the issue?
    Could you please send scope captures from both frequencies?

    Regards,
    Joel