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TFP401A-Q1: Jitter at Hsync during blanking time

Hirotaka Matsumoto
Guru 27555 points
Part Number: TFP401A-Q1
Other Parts Discussed in Thread: TFP401A, TFP401

Hi all

Would you mind if we ask TFP401A-Q1?

Could you refer to the attachment file?



In case of except for horizontal period of the input signal which is 8 multiples of CLK value,  it occurs jitter at Hsync during blanking time.
For example, Htotal + 4clk -> Htotal - 4clk -> Htotal + 4clk,,,

<Question>
Is it normal opretation?
If it is not normal operation, could you let us know the method for it?
And then, if the information we served is not enough, could you let us know?

Kind regards,

Hirotaka Matsumoto

  • 0
    TI__Mastermind 18655 points
    Hello,

    The TFP401A only de-serialize what is coming on the TMDS stream, make sure your EDID settings are correct.

    Are you sending an even number of clocks during DE high and during DE low?

    Does the TMDS data stream contain Audio?

    Does it happen at multip0le clock frequencies?

    Regards
  • 0 in reply to Joel Jimenez0
    Guru 27555 points

    Joel san

    Thank you for your reply and cooperation!
    We confirmed it to our customer.

    Our customer's EDID settings are follows;
    H-Resolution [px]    720
    V-Resolution [lines] 400
    Pixelclock   [MHz]   28.322
    H-Frequency  [kHz]   31.469
    V-Frequency  [Hz]    59.941
    H-Sync-polarity      -
    V-Sync-polarity      +
    H-Total      [dots]  900
    H-Blanking   [dots]  180
    H-Frontporch [dots]   18
    H-Sync-width [dots]  108
    H-Backporch  [dots]   54
    V-Total      [lines] 525
    V-Blanking   [lines] 125
    V-Frontporch [lines]  50
    V-Sync-width [lines]   2
    V-Backporch  [lines]  73

    Are you sending an even number of clocks during DE high and during DE low?
    ->During between DE high and DE low, our customer is sending an even number of clocks.

    Does the TMDS data stream contain Audio?
    ->No, it doesn't

    Does it happen at multiple clock frequencies?
    ->28.322MHz and 33.08MHz, in case of both multiple clock frequencies, it occurs.

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    TI__Mastermind 18655 points
    Hello Matsumoto-san,

    The TFP401A includes HSYNC regeneration circuitry that may cause this behavior in the blanking period. This was required to be Interoperable with the Sil154 that exhibited HSYNC jitter. However, the Sil154 is no longer on the market so most customers are now buying the TFP401. Could you please swap the device to TFP401 to confirm if this behavior is reproduced? If it is duplicated, it might be caused by the source.

    Regards
  • 0 in reply to Joel Jimenez0
    Guru 27555 points

    Joel san

    Thank you so much for your reply!

    Could you please swap the device to TFP401 to confirm if this behavior is reproduced?
    ->OK, we let our customer confirm it.

    Just in case, we would like to confirm one point.
    Is it posbbile to disable this behavior using register setting?
    Otherwise, unless our customer uses TFP401(without A), there is this behavior, right?

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    TI__Mastermind 18655 points

    Hi Hirotaka, 

    The TFP401/A does not support up configuration through registers. Please, try the TFP401 it should not have this behavior.

    Regards