Other Parts Discussed in Thread: DS90UH947-Q1, SN65DSI84
Hello,
I have a question about the LVDS output specification of SN65DSI84-Q1.
Channels A and B of the LVDS output of SN65DSI84-Q1 each have independent LVDS differential clocks. Are these clocks synchronized?
For example, when connecting SN65DSI84-Q1 to DS90UH947-Q1,
The DS90UH947-Q1 LVDS differential clock input has only 1 channel.
Therefore, I think that the LVDS differential clock of Channel A / B needs to be synchronized.
It is described on page 16 of the data sheet of SN65DSI84 - Q1
Figure 11. LVDS Output Data (Format 2); Dual-Link 24 Bpp,
It seems that A_CLKP / N and B_CLKP / N are synchronized.
Using this format, if either CLK of A or B is connected to CLK of DS90UH947 - Q1, can it be used without problems?
Best Regards,Orobianco
