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DS90UB925Q-Q1: FCdelay and BCCdelay

K.Yaita
Guru 29720 points
Part Number: DS90UB925Q-Q1
Other Parts Discussed in Thread: DS90UH925Q

Hi Team,

I found the following application note and would like to ask an question.
http://www.ti.com/lit/an/snla131a/snla131a.pdf
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(page 4)
Example of DS90UH925Q/926Q/UB925Q/UB926Q chipset:
For the 100 kbit/s (100 kHz) :
Host_bit = 10us (100 kHz)
Remote_bit = 13.5us (default 74 kHz)
FCdelay = 1us (max)
BCCdelay = 9us (typical value)
Effective rate = 9bits / (90us + 121us + 1us + 9us) = 40.6 kbit/s
----------------------------------------------------------------------
Could you tell me where are the value of FCdelay and BCCdelay quoted from?
It seems datasheet of DS90UB925Q and DS90UB926Q don't show these values.

Best Regards,
Yaita / Japan disty

  • 0
    TI__Genius 12705 points
    The FCdelay value is the forward channel delay required to send a byte of data or response on the forward channel. Forward channel I2C sampling frequency is dependent on the pixel clock rate. The FCdelay value is typically on the order of 1 to 2 μs dependent on the pixel clock frequency.

    The BCdelay value is the back channel delay required to send a byte of data or response on the back channel. This value is defined by the amount of time required to send 1 or 2 back channel frames, which amounts to between 7 and 13 μs at nominal oscillator clock frequencies. Since the actual delay will be random for any single transfer, an average value is used for throughput calculations.

    For the 925 and 926 I2C throughput calculations worst case should based on internal clock variation of +/30%.
    Please refer to section 5.3 on FPD-Link learning center link below for more description of the backchannel communication.

    training.ti.com/fpd-link-learning-center

    Regards,
    Liam