Linux/DP83867IS: driver with SGMII inteface not working

Hi,

To help you with debug, first I would like to confirm that your Hardware design/routing is correct. Can you please go thru DP83867 troubeshooting uide section 2.10 "Establishing SGMII link" and confirm everything is ok ?

Post this I would like to check, whether the AutoNegotiation process between SGMII and MAC is complete ?

Regards,
Geet

Hi,
we gone through the DP83867 troubleshooting guide section 2.10 "Establishing SGMII link", below are check points

1 The DP83867 includes internal SGMII terminations. No external terminations are required.
>No external termination provided.

2 All SGMII connections should be AC coupled via an 0.1-μF capacitor.
> All SGMII connections are AC coupled via an 0.1-μF capacitor.

3 Traces should be routed with 100-Ω differential impedance.
>Yes

4 Skew matching within a pair should be less than 5 pS, which correlates to 30mil for standard FR4.

part of net name Length
PHY1
SOC_SGMII2_TXP 4232.48 MIL
SOC_SGMII2_TXN 4224.35 MIL
SOC_SGMII2_RXP 3231.04 MIL
SOC_SGMII2_RXN 3254.53 MIL

PHY2
SOC_SGMII3_TXP 5702.97 MIL
SOC_SGMII3_TXN 5713.57 MIL
SOC_SGMII3_RXP 4584.06 MIL
SOC_SGMII3_RXN 4617.22 MIL

5 When operating in 6-wire mode, the RX pair must match the Clock pair to within 5 pS, which correlates
to 30mil for standard FR4.
>Operating in 4 wire mode.

6 When operating in SGMII mode, dummy straps may be necessary to provide a balanced load for the
SGMII differential pairs. Therefore, for SGMII applications with straps configured for RX_D0 and/or
RX_D2, matching terminations must be used for RX_D1 and/or RX_D3. For more details, see the PHY
Address Configuration section of the data sheet.
>Provided

7 When establishing an SGMII connection between the MAC and the PHY, both the MAC and the PHY
should have a common configuration. SGMII Auto-Negotiation is the preferred mechanism for
establishing communication. If Auto-Negotiation is not used, both the MAC and the PHY must be
forced to the same speed and duplex configuration.
> below register setting done in the dp83867.c and also attached file with query
phy_write(phydev, MII_BMCR,
(BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000)); /* ie : reg 0x0 = 0x1140 */

cfg2 = phy_read(phydev, MII_DP83867_CFG2);
cfg2 &= MII_DP83867_CFG2_MASK;
cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
MII_DP83867_CFG2_SGMII_AUTONEGEN |
MII_DP83867_CFG2_SPEEDOPT_ENH |
MII_DP83867_CFG2_SPEEDOPT_CNT |
MII_DP83867_CFG2_SPEEDOPT_INTLOW); /* ie: reg 0x14 = 0x29C7*/

phy_write(phydev, MII_DP83867_CFG2, cfg2);
phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
DP83867_DEVADDR, 0x0); /*ie : reg 0x32 = 0 */

phy_write(phydev, MII_DP83867_PHYCTRL,
DP83867_PHYCTRL_SGMIIEN |
(DP83867_MDI_CROSSOVER_MDIX <<
DP83867_MDI_CROSSOVER) |
(dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
(dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT)) /*ie: reg 0x10 = 0x5840*/

phy_write(phydev, MII_DP83867_BISCR, 0x0); /*ie: reg 0x16 = 0 */

8 Unstable MDI link can result in unstable SGMII connection. If the PHY cannot maintain a link, it can
cause the SGMII Auto-Negotiation to loop. The unstable MDI link must be resolved in order to resolve
the SGMII Auto-Negotiation loop.
> how to test................................ ?



Regards,
Gireesh Hiremath
Lekha Wireless

8 : It says, the MDI side link shall be stable to complete the SGMII Auto Neg. This can be check thru Link Status register. Further you can look at SGMII Status Register to undrestand the status of this link. "SGMII Auto-Negotiation Status :0x0037"

Then I would like to try the MAC loopback mode and check whether you are able recieve the packets back or not.

Regards,
Geet