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Linux的/ SN65DSI83EVM：sn65dsi83 to display abnormal.

xingxing Luo
Prodigy 130 points
Part Number: SN65DSI83EVM
Other Parts Discussed in Thread: SN65DSI83

Tool/software: Linux

Hi Guys:

I had used sn65dsi83 on my project, the soc is qualcomm MSM8909, and the display almost ok, but I still have a question here:

my original picture is :

but the display show:

The button of the display works abnormal, did you have any suggestion for  me?

Thanks.

B.R.

  • 0
    TI__Mastermind 18655 points
    Hello xingxing Luo,

    Could you please share the panel datasheet along with the .dsi file or DSI Tool screenshots? I would need to know your configuration.

    Please, also generate a complete register dump including the status register at offset 0xE5 and 0xE6.

    Regards
  • 0 in reply to Joel Jimenez0
    Prodigy 130 points
    LCD size: 1280*720

    /*Reset and Clock Registers*/
    {0x09, 0x00},
    {0x0A, 0x05},
    {0x0B, 0x08},
    {0x0D, 0x00},
    /*DSI Registers*/
    {0x10, 0x20},
    {0x11, 0xCC},
    {0x12, 0x20},
    /*LVDS Registers*/
    {0x18, 0x78},
    {0x19, 0x00},
    {0x1A, 0x02},
    {0x1B, 0x00},

    /*Video Registers*/
    {0x20, 0x00},
    {0x21, 0x05},

    #if SN65DSI83_TEST_MODE
    {0x24, 0xD0},
    {0x25, 0x02},
    #else
    {0x24, 0x00},
    {0x25, 0x00},
    #endif

    {0x28, 0xBB},
    {0x29, 0x02},

    {0x2C, 0x08},
    {0x2D, 0x00},

    {0x30, 0x01},
    {0x31, 0x00},


    {0x34, 0x90},

    #if SN65DSI83_TEST_MODE
    {0x36, 0x03},
    {0x38, 0x2f},
    {0x3A, 0x02},
    {0x3C, 0x10}
    #else
    {0x36, 0x00},
    {0x38, 0x00},
    {0x3A, 0x00},
    {0x3C, 0x00}
    #endif

    0xE5 is 0, and I din't found 0xE6 register.
  • 0 in reply to xingxing Luo
    TI__Mastermind 18655 points
    Hello xingxing Luo.

    Regarding your clock configuration, it seems that your DSI clk frequency is not enough to support a pixel clock of 70MHz 24bpp.
    Stream Bit Rate = PixelClock × bpp
    Stream Bit Rate = 70 × 24 = 1.680 Gbps
    Min Required DSI Clock Frequency = 1680/ (4 × 2)
    Min Required DSI Clock Frequency = 210 MHz

    Could you please use a DSI Clk frequency of 210MHz instead of 161MHz and a divisor of 3 instead of 2?

    Also, confirm the new line time requirement in the tool (output tab) and the actual line time in the GPU?

    Regards
  • 0 in reply to Joel Jimenez0
    Prodigy 130 points

    Hi Joel:

    My current DSI clk frequency is 161MHz, and divisor is 2, so the SN65dsi83 clk is 161/2 = 80.5, it was bigger than 70MHz, did I misunderstand your means?

    Anyway ,I will try your suggestion.

    B.R.

  • 0 in reply to xingxing Luo
    TI__Mastermind 18655 points

    Hi xingxing Luo,

    Please, try the attached configuration. I have set the pixel clock to 59.7MHz as per the panel's datasheet and an input DSI clock of 180MHz. 

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/HSD080_5F00_TI.dsi