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DS125DF410: EOM_GET_HEO_VEO bit for CDR lock condition

masahiko shimizu
Guru 11235 points
Part Number: DS125DF410

Hi,

My cusotmer is using DS125DF410.
He has a issue of CDR unlock (LOCKx pin is low).

His system has "the register configuration procedure" of datasheet page 16.
But He has unlock this condition.

Next, He added setting of 0x24 address = 0x42 after "the register configuration procedure".
Then, He could has lock condition.

What is the cause of this issue?
Why was this issue resolved by setting of 0x24 address = 0x42 after "the register configuration procedure"?
Could you give me advice, please?

Best regards,
Shimizu

  • 0
    TI__Mastermind 23675 points
    Hi Shimizu,

    I will move your question to the correct thread so that its receives more visibility.

    Kind regards,
    Ross
  • 0 in reply to Ross Pimentel
    TI__Mastermind 19235 points

    Hi,

    This result observed by customer does not make sense to me based on the register's definition (see below). Bit 6 is a status bit, while bit 1 simply triggers HEO/VEO measurement. What values is the customer observing for channel registers 0x03, 0x27 and 0x28?

    24

    7

    0

    RW

    N

    FAST_EOM

    1: Enables fast EOM mode for fully eye capture. In this mode the phase DAC and voltage DAC of the EOM are automatically incremented through a 64 x 64 matrix. Values for each point are stored in channel registers 25 and 26.

    6

    0

    RW

    N

    DFE_EQ_ERROR_NO_LOCK

    DFE/CTLE SM quit due to loss of lock

    5

    0

    RW

    N

    GET_HEO_VEO_ERROR_ NO_HITS

    GET_HEO_VEO sees no hits at zero crossing

    4

    0

    RW

    N

    GET_HEO_VEO_ERROR_ NO_OPENING

    GET_HEO_VEO cannot see a vertical eye opening

    3

    0

    RW

    N

    RESERVED

    2

    0

    RW

    N

    DFE_ADAPT

    1: Manually start DFE adaption, self-clearing.

    0: Normal operation

    1

    0

    RW

    N

    EOM_GET_HEO_VEO

    1: Manually triggers a HEO/VEO measurement. Must be enabled with channel register 0x23[7].

    0

    0

    RW

    N

    EOM_START

    1: Starts EOM counter, self clearing

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • 0 in reply to Rodrigo Natal
    Guru 11235 points

    Hi Rodrigo-san,

    Thank you for your reply.
    I confirmed register value.
    Do you have an idea of this event?

    [In case of not setting 0x24 address=0x42]
    -0x03 = 0xff
    -0x27 = 0x00
    -0x28 = 0x00

    [In case of setting 0x24 address=0x42]
    -0x03 = 0xff
    -0x27 = 0x29
    -0x28 = 0x8a

    Best regards,
    Shimizu

  • 0 in reply to masahiko shimizu
    TI__Mastermind 19235 points

    I still don't have an explanation for this result. What Rx adapt mode are you using (set via channel register 0x31)?

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • 0 in reply to Rodrigo Natal
    Guru 11235 points

    Hi Rodrigo-san,

    Thank you for your reply.

    My customer is setting 0x31 address = 0x20.

    Best regards,
    Shimizu

  • 0 in reply to masahiko shimizu
    TI__Mastermind 19235 points

    I would suggest to try adapt mode 2 (0x31 = 0x40). By the way, what is the aproximate retimer input channel insertion loss?

  • 0 in reply to Rodrigo Natal
    Guru 11235 points

     Rodrigo-san,

    Thank you for your reply.
    I could get customer's the procedure of register setting.
    I'm sorry for late provide this information.
    Please see the attached excel file of Sheet1.
    Something you see in this?


    >I would suggest to try adapt mode 2 (0x31 = 0x40).
    ->DFE is disable in customer setting (0x1E = 0xE9).
       Do we try this with DFE disable?
       (I'm sorry for late provide information of customer's the procedure of register setting.)

    >what is the aproximate retimer input channel insertion loss?
    ->It is about -30dB.

    Best regards,
    Shimizu

  • 0 in reply to masahiko shimizu
    TI__Mastermind 19235 points

    Hi Shimizu-san,

    Our recommended way to use DFE is to with adapt mode 2, by setting the following registers:

    • 0x31 = 0x40
    • 0x1E = 0xE1

    Based on the Excel file the customer changed some default values that I would advice against.Please revert the channel registers below to their default values:

    • 0x12, 0x15, 0x21, 0x23, 0x24

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • 0 in reply to Rodrigo Natal
    Guru 11235 points

    Hi Rodrigo-san,

    Thank you for your support.

    We tried to set default value below, then we can be lock CDR without setting of 0x24 address to 0x42.

    • 0x12, 0x15, 0x21, 0x23, 0x24

    I add question about 0x40 address.

    Customer set 0x40 address to 0xFF. 

    Is it problem?

    Best regards,

    Shimizu

     

  • 0 in reply to masahiko shimizu
    TI__Mastermind 19235 points

    Hi Shimizu-san,

    Channel register 0x40 corresponds to Rx CTLE table index 0 i.e. the first boost setting in the CTLE table. The TI retimer is intended to implement a "hill-climb" algorithm, whereby the retimer incrementally steps through the CTLE table values, moving from lowest to highest boost level. If the customer sets index 0 to 0xFF (the highest possible CTLE value)  this might adversely affect the CTLE adaption process. I would recommend to maintain 0x40 = 0x00. If the customer empirically finds that CTLE = 0xFF yields the best retimer input eye opening result for their application setup, I would then recommend to manually force that boost value via channel register 0x03.

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer