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TLK10232: LS Serdes PLL is not locked while HS Serdes PLL locked

jiandong wang
Prodigy 40 points
Part Number: TLK10232

Hi, all

In our design a 156.25MHz clock is sourced to REFCLK_0. When we check the PLL status by reading CHANNEL_STATUS_1, we find that LS_PLL_LOCK is 0, HS_PLL_LOCK is 1.

We are confused as both LS PLL and HS PLL are using the same reference clock.  Can it be that the quality of reference clock not so good? Or any other cause?

  • 0
    TI__Genius 16150 points
    Hi Jiandong,

    High and low speed sides uses the same REFCLK signal. Could you provide more information about your application? As well, how are your configuring the device (default values or different values for registers)? Please make sure the reference clock signal is meeting the clock characteristics in Section 9.7 of datasheet.

    Best Regards,
    Luis Omar Moran
    High Speed Interface
    SWAT Team
  • 0 in reply to Luis Omar Moran
    Prodigy 40 points
    Hi Luis,

    Thanks for your quick relpy!
    In our design, the low speed side (XAUI) of TLK10232 are connected to BCM56334 (broadcom switch chip) and the high speed side are connected to a SFP+ connectors. Both ST pin and MODE_SEL pin of TLK10232 are connect to ground.
    Following registers are changed (in order to work in XUAI to SFI mode):
    1E.0 0x8610 // reset device
    07.0 0x2000 // disable auto negotiation
    01.96 0x0 // disable link training
    1E.e 0x8 // data path reset

    In the design, a differential oscillator and a LVPECL clock driver (MC100LVEP14) are used to generate the 156.25MHz reference clock.
    The quality of the generated clock should be OK as they are used in another custom board succesfully.
    We are just wondering why low speed PLL is not lock while high speed PLL is locked (They are using the same reference clock) ?
  • 0 in reply to jiandong wang
    TI__Genius 16150 points
    Hello Jiandong,

    Sorry for the delayed response. For XAUI-to-SFI/XFI operation, you will need to configure the device for 10GBASE-KR mode and disable the features specific to backplane Ethernet like Clause 73 auto-negotiation and 10G link training. To do this, follow this procedure:

    1. Reset device (write a 1 to 0x1E.0000 bit 15 or assert RESET_N pin)
    2. Make sure the reference clock selection (156.25 MHz or 312.5 MHz) is correct – this is done through register 0x1E.001D bit 12 (default is 156.25 MHz).
    3. Disable auto-negotiation by writing 1’b0 to 0x07.0000 bit 12
    4. Disable link training by writing 16’h0000 to 0x01.0096
    5. Write 16’h03FF to 0x1E.8020. This allows the link settings that would normally be configured through KR training to be configured manually instead.
    6. Depending on the link conditions, you may need to change the default configuration of 0x1E.0003 and 0x1E.0004. For optical connections, we typically recommend changing HS_ENTRACK (0x1E.0004 bit 15) to 1’b1 and HS_EQPRE (0x1E.0004 bits 14:12) to 3’b101. This can be a starting point, but you may need to do some BER testing to optimize the values.
    7. Issue a data path reset by writing 1’b1 to 0x1E.000E bit 3.

    At this point the device should be properly configured.

    Thanks,
    Luis