The DP83867E device can output the RX and TX SFD to GPIO output. I want to timestamp the rising edges of both inside an FPGA. Which clock is synchronous to these outputs? I assume its RX_CLK for RX_SFD and the reference clock (XI/O) for TX_SFD ? Or is the RX_SFD and TX_SFD not having a fixed phase relationship with any of these clocks and should I try to timestamp them at the highest possible resolution to get the best precision?
Roel
