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TLK100: The reset sequence of TLK 10x

Part Number: TLK100

Hi,

For TLK100 data sheet (P.71 AC Specifications), t1 is TYP 200 μs.

I want to know the maximum value.

Is also TLK 105 the same?

 Best regards.
 Kenji

For TLK100 data sheet (P.71 AC Specifications), t1 is TYP 200 μs.
I want to know the maximum value.
Is TLK 105 the same?
  • Hello Kenji,

    The max reset deassertion time is not listed in the datasheet, so we will not be able to share that information. Can you share how this information will be used in the system?

    -Regards,
    Aniruddha
  • Aniruddha san,

    I want to know the time of t1 so that internal reset and external reset do not occur at the same time.

    According to the datasheet it is necessary to deassert Hardware RESET_N pin before 200 μs(typ).

    I appreciate your help.

    Best Regards,

    Kenji

  • Aniruddha san,

    I understand that 200 μs after power up <---> internal reset end period is an external reset prohibited section.
    However, I noticed that Hardware RESET_N pin was Low during this external reset inhibit interval.
    Sometimes TLK100 is locked.
    After power-on reset, lock is released. Other reset is not accepted.

    Please tell me the mechanism inside the IC that will lock up.

    Best Regards,

    Kenji