Hello,
one pulse signal is LVDS interface, but the interface to receive the pulse signal is HSTL/SSTL, which device can implement it?
the min width of pulse signal is 1.8ns, the min period of the pulse signal is 2 second.
Thank you,
K
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Hello,
one pulse signal is LVDS interface, but the interface to receive the pulse signal is HSTL/SSTL, which device can implement it?
the min width of pulse signal is 1.8ns, the min period of the pulse signal is 2 second.
Thank you,
K
Hi Kerb,
A passive circuit is usually used to interface an LVDS output to a HSTL input. Please see https://e2e.ti.com/support/clocks/f/48/t/618723