SN65LVCP408: Questions on output lane-to-lane skew optimization and switching input selection

Below are the requirements and information that’s not in the datasheet and I’d to get asap.

1. Differential clock switching (1MHz to 500MHz)
2. Any input to any output
3. Any input to any groups of outputs (including all outputs)
4. Maintain output-to-output skew per specs (max 75ps) for outputs with same input source
5. Local Clock Switching: 8 in x 8 out. Best fit found on TI website is SN65LVCP408 (75ps).

Q1: Can I turn off Equalization/Pre-emphasis for better skew?

Q2: Do you have 3*sigma skew number for the chip? It should be less than 75ps.

1. Output frequencies can change on the fly when switching frequency sets

a-       No glitch is allowed for outputs with no frequency change

Q3: Is each output mux (circled in red below from p.2 of datasheet) completely independent of the others?

b-      Glitch is ok if input changes frequency

c-       Glitch is ok if output selects a new input         

1. Also need bigger Clock Switch: 18 in x 32 out

Q4: Does TI have any Crosspoint Switch to meet this large switch requirement?

Thanks,

Quang