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DS90UB953-Q1: DS90UB954-Q1 , latency between CSI input to Dout and Dout input to CSI output

Guru 20090 points
Part Number: DS90UB953-Q1

Hello,

Could you please let me know the timing chart which include following timing?

953 CSI input to DOUT+/- output
954 DIN+/- input to CSI output

Are there any timing requirement between PDB high to input valid CSI data?

I appreciate it you would help this post.

Best Regards,
Ryuji

  • Hello,
    We have received your inquiry and are investigating best how to reply. The CSI-2 as it is packet based can vary in timing.

    There is no constraint on PDB high to when valid CSI-2 data must be present as the link is reference to either the backchannel frequency REF_CLK or external CLK_IN
  • The latency depends greatly on the CSI-2 packet type and line size being processed as well as the CSI-2 input frequency and CSI-2 output frequency. We do not have the specific timing you requested, but for a typical 953-954 running at 4 Gbps, 800Mbps per lane input and 1600 Mbps per lane output the approximate latency for a line size of 1280 pixels would be 20us from 953 CSI input to 954 CSI output. You can get a pretty good estimate of the latency for your particular system by configuring the 954 to bring the FV/LV to GPIOs and comparing that to the LP/HS transition on the CSI-2 signals.