• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 33 subscribers
  • Views 744 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN65LVDS109: SN65LVDS109

Hen
Expert 1070 points
Part Number: SN65LVDS109
Other Parts Discussed in Thread: SN65LVDS100

Hi,

I need to know what is its allowable difference between the A and B lines to not cause any problems, i.e. the tolerance between the A and B to the chip lines on the PCB editing, the chip is driving 40MHz clock.

Please advise.

 

Thanks

  • 0
    TI__Intellectual 2915 points
    Hi,

    Can you elaborate more on your question? Are you asking about your design margin or layout specific? We are unclear about questions on the PCB editing.

    Dennis
  • 0
    TI__Intellectual 1810 points

    Hi Yossi,

     

    I hope you’re asking about the maximum intra-pair skew (between P and N signals) that the SN65LVDS100 device can handle at its input. Please confirm.

     

    If the above is correct, then the device really doesn’t care about the intra-pair skew at its input (A and B pins) as long as the input voltage is within it input threshold limits. An input signal with intra-pair skew will result in an output signal also with an intra-pair skew. You should be concerned at the system level with a clock signal that has intra-pair skew since that can result in duty-cycle distortion and affect your timing. It will also give rise to a high common-mode voltage that is not good for EMI (electromagnetic interference).

     

    Best regards,

     

    Hassan.

  • 0 in reply to HA
    TI__Intellectual 2915 points
    Hi Yossi,

    Please mark this post as answered via the Verify Answer button below if you think it answers your question. Thanks!

    Dennis