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DP83822I: Timing of Hardware Reset de-assertion

Guru 15520 points
Part Number: DP83822I
Other Parts Discussed in Thread: TLK105L

Hi,

I have a question about DP83822I reset timing.

From the datasheet of DP83822I, I couldn't find the timing specification
between VDDIO/AVD and Hardware RESET_N.
Are there any timing specification between VDDIO/AVD and Hardware RESET_N?

What I want to know is,
does Hardware RESET_N need to be deasserted after VDDIO/AVD have been stabilized?
If yes, how long should RESET_N need to be assert after VDDIO/AVD have been stabilized?

From the datasheet of DP83822I, I couldn't find the above timing specification.

best regards,
g.f.

  • Hi g.f.

    The RESET_N pin does not need to wait for supplies to become stable. An internal reset is generated when the VDDIO/AVDD supplies are ramped up.

    The POR time is typically 200ms and follows the timing shown in the Power-Up Timing time T2 when measured from supply ramp up and RESET is pulled high.

    Best Regards,
  • Hi Rob,

    Thank you for the reply and I understood that there are no timing specification between VDDIO/AVDD and RESET_IN.
    But sorry, I have a few additional question about DP83822I reset.

    >"An internal reset is generated when the VDDIO/AVDD supplies are ramped up."
    Q1.
    Do you mean that internal reset be generated even if RESET_N kept asserted after power are ramped up?
    Or does RESET_N also need to be deasserted for internal reset be generated?


    Q2.
    Does RESET_N and internal reset(POR) will force same reset process?

    Q3.
    What is the use case of RESET_N?
    Is it optional and can be always tied to High(deassert) if hard reset for DP83822 are not required
    during normal operation?

    Q4.If I don't use RESET_N, can it be left floating because it has internal Pullup?

    Q5.
    The description of RESET_N in DP83822i datasheet page.5 Pin Function table,
    it said as follow:
    *****************************************************************************
    Asserting this pin low for at least 1μs will force a reset process to occur.
    *****************************************************************************
    But Reset Timing table in page.11, it said RESET pulse width is 10μs(Min).
    Which is true? Is it 1μs?

    best regards,
    g.f.
  • Hi g.f.

    Q1. Yes, even if RESET_N is kept asserted after power up, the internal POR still occurs.

    Q2. Yes, they force the same process.

    Q3. RESET_N can be used if any error occurs with the device during normal operation. Sometimes it is used by customers to restart auto-negotiation when a link is not present.

    Q4. It can be left floating.

    Q5. I have to look into this.

    Best Regards,
  • Hi Rob,

    Thank you for answering to my questions.
    I understood about Q1-Q4.

    About Q5, in other TI EtherPhy Product (ex. TLK105L, DP83848, DP83867),
    the RESET pulse width is 1μs(Min), so I'm guessing DP83822 RESET pulse width is also 1μs(min) .
    But I will wait for the answer from you.

    best regards,
    g.f.
  • Hi g.f.

    During characterization of the DP83822, the reset pulse width was determined to be 10us. If this is difficult for your system to deal with, 1us is usable but outside the guarantee of the datasheet.

    10us is not a typo.

    Best Regards,
  • Hi Rob,

    Thank you for the reply.
    I understood.

    best regards,
    g.f.