• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 611 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB914A-Q1: Behavior of Parity function

Ryuuichi machida
Guru 12650 points
Part Number: DS90UB914A-Q1

Hi,

I would like you to confirm about below.

* If parity error value of address 0x1A and 0x1B of DS90UB914A-Q1 exceed value of 0x18 and 0x19 (threshold of parity error), which register or pin indicate this ?

Best Regards,

  • 0
    TI__Genius 12866 points

    Hi,
    The counter in 0x1A and 0x1B are saturating counters. The max limit they will count up to is the threshold set in 0x18 and 0x19, and will stay at the threshold even if there're more errors.

    Editing to clarify. The PASS pin will go low every time there is a parity error, so if the 0x1A and 0x1B saturates, you could monitor PASS pin to check parity error. 

    Sincerely,
    Charley Cai

  • 0 in reply to Charley Cai
    Guru 12650 points

    Hi Cai-san,

    Thank you for your reply.

    I understood how 0x1A and 0x1B will count up.

    Let me confirm about relationship b/w "Parity error" bit of 0x1C[2] and "0x1A and 0x1B".

    I guess following behavior will happen.

    *

    --

    Case 1 :
    When pariry error occur for the first time.

    * 0x1C[2] will be asserted and "PASS" pin will become "LOW". Also, count up 0x1B register.

    Case 2 :
    When pariry error occur many times.

    * 0x1C[2] will continue to be asserted and "PASS" pin will keep "LOW".
      Also, when counter value of 0x1A and 0x1B become equal to 0x18 and 0x19, counter of 0x1A and 0x1B will stop.

    --

    if there is any other expected behavior, could you please let me know ?

    Best Regards,

  • 0 in reply to Ryuuichi machida
    TI__Genius 12866 points

    Hi,

    Case 1 :
    When pariry error occur for the first time.

    * 0x1C[2] will be asserted.                    Yes

    * "PASS" pin will become "LOW".         No, PASS pin will transit from "HIGH" to "LOW" then back to "HIGH"

    * Also, count up 0x1B register.              No, 0x1A register will count up first because it is the least significant byte. 

    Case 2 :
    When pariry error occur many times.

    * 0x1C[2] will continue to be asserted           Yes

    * and "PASS" pin will keep "LOW".                No, every time there is a parity error, PASS pin will transit from "HIGH" to "LOW" then back to "HIGH"
     * Also, when counter value of 0x1A and 0x1B become equal to 0x18 and 0x19, counter of 0x1A and 0x1B will stop.    Yes

     

     

    Sincerely,

    Charley Cai