Hi,
Disclaimer: I'm a new user of serdes chips and video streams over FPDLink etc.
I have a 953 and 934 serdes pair connected up and I'm trying to get the pattern generator on the 953 working.
With a very basic I2C init script, I've found that I need to disable the RX_PARITY_CHECK_ENABLE bit on the BCC register (0x32) on the 953 to get the pattern generator working.
I suspect it's probably unrelated to the pattern generator and more likely related to the overall back-channel comms working or not working.
My question is, what exactly is that configuration bit doing, and is turning off parity checking a bad thing?
I can't seem to find a matching "enable parity" on the 934 chip, only a BCC CRC generation enable bit on register 0x58 (which is set to enable), and there is not much explanation anywhere else (that I can find) for that bit.
Is this just a nomenclature mix-up and it should be CRC checking enable on the 953? If so, and I have CRC generation turned on, is disabling the parity check a bad thing? :)
A brief explanation (or url to an appropriate app note/etc.) would be greatly appreciated :)
Cheers,
Kyle
