TLK10031: TLK10031's XAUI transceiver sync and alignment problem with FPGA XAUI core

Hi,

Our system setup with the TLK10031 as shown below.

We want to operate TLK10031 at 10GBASE-KR mode. No optical module/cable.

The following is what I tried;

1. On FPGA side, loopback mode is enabled with XAUI transceivers
2. FPGA side status signals for XAUI transceivers indicate that the RX Alignment and sycn for all four channels go up meaning that loopback mode is working
3. FPGA side XAUI TX aligned signal also gone up, of course.
4. As many bytes as I push to XAUI interface with in FPGA, I get all of them back.

Now that I confirmed that FPGA side XAUI transceivers work in loopback mode, I disabled the loopback mode so that it can communicate with TLK10031 (Until now TLK10031's RESETN is kept at active low)

By reading the TLK10031 datasheet and different TI's E2E forum posts the following is done

1. In our PCB, TLK10031’s ST, MODE_SEL, PDTRXA_N and RESETN are tied to GND through individual 1k resistors. So after power up of the board,
2. we drive the RESETN pin to low from FPGA (just to make sure, resetn is active low after power rails are stabilized). We also drive ST and MODE_SEL pins to low.
3. drive PDTRXA_N to high
4. wait for some arbitrary amount of time (which is more than 10 us requirement of RESETN)
5. drive RESETN pin to high.
6. Is there anything wrong so far?
7. 
   
8. Issue a software reset through MDIO by setting 0x1E.0 bit 15 to 1
9. Is there any time we need to wait before proceeding with further MDIO read/write operation?
10. 
    
11. Through MDIO 0x1E.2 bits 3:0, set the HS_PLL_MULT bits to 0xC per table 7.1 of datasheet
12. Making sure that 156.25MHZ is the reference frequency by reading 0x1E.1D bits 13:12
13. Issue a reset to data path by writing 1 to 0x1E.E bit 3 (all other bits are written with their old values)
14. Check at the FPGA side XAUI status registers. No RX align or sync bits are set to 1. Does not it mean that there is no communication between FPGA transceivers and TLK10031 low speed side transceivers?
15.  
16. I followed the steps again from 1 to 14 and then enabled shallow loopback by writing 1 to 0x1E.B bit0 (all other bits of the registers are written back with same value as read)
17. Issue a reset to data path by writing 1 to 0x1E.E bit 3 (all other bits are written with their old values)
18. Check at the FPGA side XAUI status registers. No RX align or sync bits are set to 1. Does not it mean that there is no communication between FPGA transceivers and TLK10031 low speed side transceivers?

Questions:

1. How can make sure that TLK10031's Low speed side transceivers are working as expected?
2. What should I do to test the TLK10031’s low speed side in loopback mode?
3. It appears that the 10GBASE-KR side chip is also not in communication with TLK10031.
4. Does not having the 10GBASE-KR side link up, prevent low side transceivers NOT to go online with the FPGA’s XAUI transceivers?
5. If I put the TLK10031 in high speed side shallow loopback mode, what is that I should I do to make the TLK10031’s 10GBASE-KR side to bring its lane/link up with its 10GBASE-KR partner?
6. Do I need to worry about LS_OK_IN_A  pin in 10GBASE-KR mode? Does it need to be driven with a particular value when RESETN is asserted high? I am not sure what the datasheet means by proprietary pattern for LS_OK signal.
   
7. I have driven LS_OK_IN_A continuously at ‘1’ before and after resetn to ‘1’. No rx lane sync or alignment at FPGA side. I drove LS_OK_IN_A continuously to ‘0’ before and after resetn to ‘1’. Still no lane up on FPGA side.
8. How do I know TLK10031 on its low speed side receivers syncs on each lane from FPGA? How to information FPGA's XAUI core that TLK10031 has sync and aligned on all four XAUI lanes?

Thank you in advance for your time and support!