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DP83867IR: Transmitter Clock Source

Michael Fauth
Prodigy 70 points
Part Number: DP83867IR

Hi all,

i am working on a system that requires clock synchronization over Ethernet. On the receiver side i think this task is easy to achieve - i am going to use the  "CLK_OUT"-Pin to output the recovered receive clock. On the transmitter side i am not sure how the PHY works. Is the transmitter clock derived from the "TX_CLK" Signal as it is part of the RGMII Interface (Option A)? Or is the transmitter clock derived from the "XI" Input (Option B)?

If option A is the case i can use a simple free-running crystal to provide the "XI" Signal. For Option B i can't use a crystal for XI. Instead i have to provide a clock which is derived from other clocks in the system.

Best Regards

Michael

  • 0
    TI__Mastermind 19780 points
    Hi Michael,

    There is some discussion about the use of Synchronous Ethernet in this app note: www.ti.com/.../snla100a.pdf

    If the accuracy requirement for your clock synchronization is not that tight, us to ms TIE needed, then you may want to disregard the use of synchronous clock domains in order to keep from using an external PLL.

    To answer your question tho, the DP83867 transmit clock, when in 1000M master mode is derived from the XI signal. In 1000M slave mode, the transmit clock is recovered from the master's transmit clock.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 70 points
    Hi Rob,

    thanks for your quick response. I am going to provide a PLL derived clock to the XI input. A PLL is on the PCB anyway, so this is not a problem.

    Best Regards
    Michael