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DP83867IR: RGMII Interfacing Timing Budget

Zhou Fang67
Expert 4250 points
Part Number: DP83867IR

Hi Expert,

We are dealing with RGMII timing design, try to fully understand timming budget for RGMII interfacing between MAC & DP83867. There are several questions need to be double check:

1. In DP83867IR datasheet, Figure 4, RGMII has TskewR & TskewT. However, in app note, "RGMII Interface Timing Budgets", Figure 2 shown TsetupR & TholdR. There is no TskewR and TskewT any more. So, we need to refer both Figures for Tskewx, Tsetup & Thold?

2. In app note, "RGMII Interface TIming Budgets", Table 1. The TsetupR is 1ns ~ 2ns, TskewR is 1ns ~2.6ns. How to consider the difference between TsetupR and TskewR? They looks almost the same from timing diagram.

3. In app note, "RGMII Interface TIming Budgets", Table 1. Why TskewT has both positive and negative value, but TskewR only has positive value? TskewR is introduced by DP83867 internal receiver buffer?

4. Why does the Figure 3 & Equiation (1) in app note ignore TskewR? If TskewR is considered, then there will be more margin for MinSR and less margin for MinHR?

Thanks.

Zhou

  • 0
    TI__Mastermind 19780 points
    Hi Zhou,

    I hope this clarity answers your questions.

    TsetupR and TholdR is the main spec that needs to be met to ensure the receiver has time to properly latch the data when the clock pulse comes. Tskew(T or R) is mismatch between clock and data lines on the RGMII. This is because a source synchronous transmitter will have some delay between clock and data that cannot be controlled.

    Thus TskewT & TskewR can be positive or negative. For simplicity, TskewR is only shown as positive.

    The receive buffer can introduce skew, but that does not need to be covered by the RGMII spec. The skew of the receive buffer is a challenge for the IC designers.

    In the diagrams in the app note, it is intended to show that components of skew, and setup need to be considered at the same time to effectively analyze your timing setting.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    TI__Expert 4250 points
    Hi Rob,

    Thanks for your information.

    One more confusion is that TskewT = -500ps to 500ps.
    TsetupT = 1.2ns(Typ 2ns)

    TsetupT is violated if clock and data are aligned. How can I interpret this for RGMII?

    Thanks.
    Zhou
  • 0 in reply to Zhou Fang67
    TI__Mastermind 23675 points
    Hi Zhou,

    The number that is important to you is TsetupR and TholdR.
    TsetupT and TholdT are relevant for the MAC.
  • 0 in reply to Ross Pimentel
    TI__Expert 4250 points

    Hi Ross,

    Thanks for your reply.

    For TX timing, TsetupT and TholdT are for MAC.

    Because for RGMII RX timing, transmitter is PHY, receiver is MAC.
    So for RX timing, TsetupT and TholdT are also relevant for PHY?

    If TsetupT is required for RXC and RXD, why RXC and RXD can be aligned? What we can think about is that aligned mode can be used with GMII.

    Or we are misunderstanding the diagram. Please help to point out our mistakes.


    Thanks.
    Zhou

  • 0 in reply to Zhou Fang67
    TI__Mastermind 23675 points
    TsetupT and TholdT are not useful parameters. These should not have been included in the datasheeet.
    What is important is your min setup and min hold...i.e. TsetupR and TholdR.
    TsetupR is the min setup that the receiver at both the PHY and MAC can handle.
    TsetupT is saying what the delay is of the clock from the transmitter.

    I will inform my team to update the datasheet and remove TsetupT and TholdT.