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SN65DPHY440SS: Register 0x70 and 0x71 function

user4555320
Prodigy 20 points
Part Number: SN65DPHY440SS

Hello,

I'm using SN65DPHY440SS retimer in 4-lane configuration with FPGA.
To pass HS signal through DA0P/N lane, like other posts in this forum,
I set value in registers that are not referred by datasheet, such as reg 0x50, 0x51, 0x70.

I found that some boards work well only when setting value 0x05 (not 0x01) into register 0x70 and 0x71.
It didn't work well when 0x01 is written in these registers.
So I want to know the function of bit 2 of register 0x70 and 0x71.

Is it possible to tell me detailed description of these registers?


Best regards,

  • 0
    TI__Mastermind 18655 points
    Hello,

    We are getting the details for you. I will come back with our answer shortly.

    Regards
  • 0 in reply to Joel Jimenez0
    TI__Mastermind 18655 points
    The 0x70.0 is the HSRX0_TERM_OVR. When this field is set to a one, then software can override the HS receiver termination settings for Lane 0.
    The 0x71.1 is the HSRX0_TERM_EN. This field reflects the state of the termination control for Lane 0. When HSRX0_TERM_OVR is one, software can directly control the termination, HS receiver, and ndatapath for receiver Lane 0.
    The bit 1 corresponds to Lane 1, bit 2 to Lane 2, bit 3 to Lane 3, bit 4 to clock lane.

    The reason to enable HS path always for Lane 0 is because lane 0 has DSI backchannel. The other lanes do NOT have a DSI back channel. If customer connects Lane 0 to a non-compliant CSI or DSI sink (like a fpga), the DPHY440 may enable LS backchannel.

    Regards
  • 0 in reply to Joel Jimenez0
    Prodigy 20 points

    Hello, Joel

    Thank you for your reply. Your information was helpful for me.

    Now I'm trying to connect FPD-Link deseriarizer's MIPI output and FPGA (non-complient receiver), requiring both LP and HS signals, via DPHY440.
    I tried these setting:
    0x61 <- 0x1F
    0x70 <- 0x01
    0x71 <- 0x01
    But the waveform of lane 0 seems to be somewhat different from other lanes, and as the result decoding of lane 0 MIPI signal sometimes failed.
    So I want to know if lane 0 can behave exactly same as other lanes.
    (in other words, disabling backchannel function of lane 0 and pass HS signal to always terminated lane 0)
    If possible, could you tell me good registers configuration?

    So far, I tuned every registers, and found that lane 0 appears to work the same as other lanes after setting these values:
    0x61<-0x1F
    0x96<-0x76
    0x97<-0x01
    Is this setting adequate?

    Best regards,

  • 0 in reply to user4555320
    TI__Mastermind 18655 points
    It will be enough by seting the below values:

    Write Register 0x50 with 8’h01 //Override enable for HS TX path
    Write Register 0x51 with 8’h01 //HS TX path enabled.
    Write Register 0x61 with 8’h00 // Disable LP path.
    Write Register 0x70 with 8’h01 //Override enable for HS RX path
    Write Register 0x71 with 8’h01 // HS RX path enabled.

    Do not change the address 0x97. The address 0x96 configures the internal regulator capabilities, so it does not have to do with the Lane 0. And the address 0x61, enable the LP path on each lane.

    Regards