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DS90CR217: Error in data transmission with DS90CR217

Bilal Malik
Prodigy 270 points
Part Number: DS90CR217
Other Parts Discussed in Thread: DS90CR218A

Dear Team,

My customer is facing an issue with the DS90CR217 regarding data transmission.

You can see below the detail of the issue, sent by my customer : 

============================================================================

I use serial interface Channel Link with the components DS90CR217 and DS90CR218.

The receiver DS90CR218 is connected to the transmitter DS90CR217 through 9m of Ethernet S/FTP CAT6 cable (differential impedance: 100 ohms).

The differential traces on PCB and the termination resistors are 100 ohms.

This configuration doesn't work.

Indeed, the received data have many errors compared to the generated data.

I have to extend the clock pair of 10cm compared to the 3 pairs of data, in order the have a correct reception.

Do you have any advice on this problem?

What is the maximum length that you have tested with those components? And what kind of cable did you use?

============================================================================

Could you please help us with that.

Thanks in advance for your help.

Best regards,

Bilal MALIK

  • 0
    TI__Intellectual 2915 points
    Hi,

    Can you send the system block diagram and schematic to us? Cat6 cable should provide a good result.
    The clock and data need to have match trace length in Channel Link I devices.

    Many times the de-serializer is not the cause of the problem, but where the problem is observed. In order to help debug the issue, information is required throughout the data path:
    - Do you have jitter characteristics of the clock source? This would be PCLK input to the serializer.
    o What clock source are you using? Have you tried to change to a clean clock source? What are the results?
    - What are the characteristics of the cable(s)? Do you know the attenuation / loss of the cables?
    o You mention using on 9m cables . Have you tried to reduce the cable length? What are the results?
    - Is the layout optimized for 100 ohm differential impedance?
    - Have you observed the LOCK output of the deserializer? Does the device become unlocked when you observe the display jittering?
    - Is the board optimized for high frequency in PCB layout and the choice of RF capacitors?
    - What are the setup condition and register settings on both Serializer and Deserializer?


    Regards,
    Dennis
  • 0 in reply to Dennis Wu
    Prodigy 10 points

    Hi,

    Following a bloc diagram: 

    The hardware board is routed with 100 Ohm differential impedance traces, between internal power planes and with controlled lengths.

    The clock source is SAW oscillator, through a FPGA. His jitter is 3ps RMS (25ps pp).

    The characteristics of cable are: SFTP, Cat6/Class E, 100 Ohm impedance. No information on attenuation.

    But the problem is not the quality of the LVDS signal on receptor, I actually tested with shorter cables (1m) and it works.

    I characterized the transmission cables and determined that the propagation time is frequency dependent. Actually, the Channel Link drive signals at different frequencies: clock and data.

    I have determined that the factor that most reduces my reception margin is this difference in propagation time between the clock and the data in the cable.

    I tested with shorter cables (1m) and it works. The longer the cable, the greater the difference in propagation time is important.

    The original purpose of my question is to know if you have ever encountered this problem.

    What is the maximum length on which you have tested these components? With what kind of cable?

    Regards

    Gérald

  • 0 in reply to Pozo Gerald
    TI__Intellectual 2915 points
    Hi,

    DS90CR217 and DS90CR218A are Channel Link I SerDes devices. Customer often has connection issues on 3 data + 1 clock pairs. In order to make sure there is no channel to channel skew on the data transmission, equal trace length is most required on all data and clock pairs. Do you have the eye diagram on all data and clocks at the outputs of transmitter and the inputs of receiver? Any Signal Integrity issues such as ringing, hitches on the signals? Do you see any channel to channel skews? Yes the propagation delay is frequency dependent. What is the PCLK are you running?

    With the application like yours, we suggest you look into channel link II SerDes devices. You have long cable reach close to 10m. The CR218A receiver doesn't have the integrated EQ (equalizer) to help you clean up jitters at the receiver side. The channel link I devices are sensitive to trace lengths on PCB and cables.

    I'm assumed you are running high speed at > 60MHz. Page 8 of datasheet has some useful information on high speed/ long distance applications. Datasheet says "Twin-coax for example, has been demonstrated at distances as great as 5 meters and with the maximum data transfer of 1.785 Gbit/s." This is assuming you are running at speed. Unfortunately, I can't locate char data on this device because of the age of this SerDes.

    The cable skew needs to remain below 90ps (@ 85 MHz clock rate) to maintain a sufficient data sampling window at the receiver

    If you have concern to publish eye diagrams on the E2E, you can send the eye diagrams and any waveform to your regional TI field apps team then forward it to me.

    Thanks,
    Dennis