Other Parts Discussed in Thread: DS32ELX0124, DS32EL0421, DS32ELX0421
Dear TI,
I have a design based around Xilinx Spartan3A-DSP, DS32EL0124 and DS32EL4210. In its current form the hardware/firmware implements an sFPDP protocol over fibre at 1.25Gbps. The PCS (8b/10b decoding) was done in FPGA because of the need the handle more K control characters than the DS32EL0124.
I want to now upgrade by replacing the sFPDP with Ethernet, joining the fiber to an external 1000BASE-X media converter (which uses a Marvell 18E1111). I can view the recovered 10bit word from the DS32EL0124 LVDS DDR using an logic analyser in the Spartan and I can read/write to any DS32EL0124 register via SMBus.
With the media converter powered, I can see that the DS32EL0124 PLL has locked up ... so I assume 1000BASE-X is continually sending comma characters.
On the logic analyser I can see the 10bits from LVDS DDR:
With Remote Sense disabled and the DC Balance disabled I get random data.
With Remote Sense disabled and the DC Balance enabled I get all zeros.
The first case is explained in data sheet:
“When both Remote Sense and DC-Balance are disabled, RS and DC_B pins set to high, the LVDS lane alignment is not maintained. In this configuration, data formatting is handled by an FPGA or external source. In this mode the deserializer locks to incoming random data.”
However, the second case would puts a requirement on the external transmitter:
“ ... where DC-Balance is enabled and Remote Sense is disabled, with RS set to high and DC_B set to low, an external device should toggle the Data Valid input to the serializer periodically to ensure constant lock. With these pin settings the devices can interface with other active component in the high speed signal path, such as fiber modules. Every time a DS32EL0421/DS32ELX0421 serializer establishes a link to a DS32EL0124/DS32ELX0124 deserializer with DC-Balance enabled and Remote Sense disabled, the Data Valid input to the serializer must be held high for 110 LVDS clock periods. This allows the deserializer to extract the clock and perform lane alignment while skipping the LINK ACQUISITION state.”
My questions are:
1) Am I correct in thinking that 1000BASE-X sends enough comma characters for DS32EL0124 to perform lane alignment when set to use DC-balance ?
2) With DS32EL0124 set to use DC-Balance I can see all zeros on the logic analyser. Can I trust this means that the Data Valid signal (RxOUT4) is low and that the other data has been successfully decoded using the 8b/10b coding scheme?
3) It could be that my FPGA logic is inverted and that the 10bits should be all ones signifying that an invalid 8b/10b code was received. Is there a way to assert a known value or sequence onto the LVDS DDR interface to check that the FPGA is receiving correctly?
Kind regards
Paul
In the case where DC-Balance is enabled and Remote Sense
is disabled, with RS set to high and DC_B set to low, an external
device should toggle the Data Valid input to the serializer
periodically to ensure constant lock. With these pin
settings the devices can interface with other active component
in the high speed signal path, such as fiber modules.
Every time a DS32EL0421/DS32ELX0421 serializer establishes
a link to a DS32EL0124/DS32ELX0124 deserializer
with DC-Balance enabled and Remote Sense disabled, the
Data Valid input to the serializer must be held high for 110
LVDS clock periods.
