Hi team,
In our usage, the differential input signal may be input while the Vcc pin is in the high impedance state or 0V pulling GND.
At this time, I am going to check whether the device will not be destroyed or whether abnormal output will occur.
So, I am looking at 8.1 Absolute Maximum Ratings(1) and 10.3.1.6 Receiver Equivalent Schematic in the datasheet.
I do not have a risk of breaking if the differential input is less than 4.3 V and I realize that High immpedance does not cause problems especially since the input terminal is only the MOS gate and the diode to the GND side.
However, I am concerned that absolute maximum input voltage is 0.3V higher than Vcc's one that is 4V.
Although there is not in the Receiver Equivalent Schematic, is there a diode in Vcc for ESD protection?
If so, I think that the input voltage always needs to be less than Vcc + Vf.
Best regards,
Tomoaki Yoshida